An inverter-based analog front-end for a 56-Gb/s PAM-4 wireline transceiver in 16-nm CMOS
K Zheng, Y Frans, SL Ambatipudi… - IEEE Solid-State …, 2019 - ieeexplore.ieee.org
This letter describes an inverter-based analog receiver front-end that was evaluated within a
complete ADC-based 56-Gb/s four pulse-amplitude modulation wireline transceiver system …
complete ADC-based 56-Gb/s four pulse-amplitude modulation wireline transceiver system …
A PAM-8 wireline transceiver with linearity improvement technique and a time-domain receiver side FFE in 65 nm CMOS
This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with
receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization …
receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization …
Analog I/Q FIR filter in 55-nm SiGe BiCMOS for 16-QAM optical communications at 112 Gb/s
M Verplaetse, J Lambrecht… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
We propose a novel implementation of a complex analog equalization filter for the
compensation of frequency-dependent variations in coherent optical links. The analog …
compensation of frequency-dependent variations in coherent optical links. The analog …
A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS
K Zheng, Y Frans, K Chang… - 2018 IEEE custom …, 2018 - ieeexplore.ieee.org
A 56 Gb/s inverter-based continuous time linear equalizer (CTLE) in 16 nm FinFET CMOS is
presented. The inverters are biased with a regulated ground supply, using a ring oscillator …
presented. The inverters are biased with a regulated ground supply, using a ring oscillator …
A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS
This article presents a compact 2× time-interleaved switched-capacitor (SC) digital-to-
analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and …
analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and …
Modeling of ADC-based serial link receivers with embedded and digital equalization
Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful
digital-domain equalizers and support multilevel modulation schemes. This paper presents …
digital-domain equalizers and support multilevel modulation schemes. This paper presents …
An SoC FPAA based programmable, ladder-filter based, linear-phase analog filter
J Hasler, S Shah - IEEE Transactions on Circuits and Systems I …, 2020 - ieeexplore.ieee.org
This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance
amplifiers as an approximate delay stage implemented on a large-scale Field …
amplifiers as an approximate delay stage implemented on a large-scale Field …
A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE
W Han, Y Wang, J Wang - IEICE Electronics Express, 2021 - jstage.jst.go.jp
This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate
receiver based on amplitude rectification. Compared with the conventional three-comparator …
receiver based on amplitude rectification. Compared with the conventional three-comparator …
A 10-Gbps continuous-time linear equalizer for mm-wave dielectric waveguide communication
The data rate-times-distance product in mm-wave dielectric waveguide (DWG)
communication links is usually limited by waveguide dispersion. This letter presents the …
communication links is usually limited by waveguide dispersion. This letter presents the …
[图书][B] System-driven circuit design for ADC-based wireline data links
K Zheng - 2018 - search.proquest.com
In the era of connectivity, wireline I/O has been a key technology underpinning the
aggressive performance improvements of computer and communication systems. All …
aggressive performance improvements of computer and communication systems. All …