An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices
S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices
R Yadav, SS Dan, S Vidhyadharan, S Hariprasad - Silicon, 2021 - Springer
This paper investigates a method to suppress the ambipolar current I amb effectively,
enhance the device performance with higher on current I on, lower off current I off, lower …
enhance the device performance with higher on current I on, lower off current I off, lower …
Performance evaluation of stacked gate oxide/high K spacers based gate all around device architectures at 10 nm technology node
In this paper, we have done performance evaluation of different Gate All Around (GAA) FET
device structures using gate-oxide stacking and spacers of different materials including dual …
device structures using gate-oxide stacking and spacers of different materials including dual …
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
S Vidhyadharan, SS Dan, SV Abhay, R Yadav… - Integration, 2020 - Elsevier
This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-
overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have …
overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have …
A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic
Q Chen, L Yang, J Li, D Wang, Z Qi, X Yang… - Microelectronics …, 2024 - Elsevier
In this work, we propose a novel hetero-junction hetero-gate-dielectric gate over source-
channel overlap dual-gate TFET with an insulator pocket and a lateral source contact (IP …
channel overlap dual-gate TFET with an insulator pocket and a lateral source contact (IP …
Low and High Vt GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications
R Yadav, SS Dan, S Hariprasad - IETE Technical Review, 2022 - Taylor & Francis
This work reports low and high threshold gate-overlap tunnel FET (GOTFET) devices for
ternary logic applications. An iterative numerical algorithm was developed, which optimises …
ternary logic applications. An iterative numerical algorithm was developed, which optimises …
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
S Vidhyadharan, SS Dan, R Yadav… - Microelectronics Journal, 2020 - Elsevier
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an
advanced TFET engineered to yield around double the on current I on, while the off current I …
advanced TFET engineered to yield around double the on current I on, while the off current I …
Analysis and Reduction of GOTFET Capacitances Using Physics-Based Compact Modeling
R Yadav, SS Dan, RM Vemuri - … Symposium on VLSI Design and Test, 2023 - Springer
This work investigates a method to suppress the gate capacitance C g as well as the
ambipolar conduction I amb of the Gate-Overlap Tunnel FETs (GOTFETs) while …
ambipolar conduction I amb of the Gate-Overlap Tunnel FETs (GOTFETs) while …
Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance
H Simhadri, SS Dan, R Yadav… - International Journal of …, 2021 - Wiley Online Library
This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device
optimized for superior analog performance. DGLTFET has thrice the on currents I on, at least …
optimized for superior analog performance. DGLTFET has thrice the on currents I on, at least …
[PDF][PDF] Superior Analog, Digital, and Ternary Circuit Designs Using Advanced Nano-electronic Gate Overlap Tunnel FET Devices for Ultra-Low Power Applications
S Hariprasad - 2023 - dspace.bits-pilani.ac.in
Energy efficiency limit has become the main obstacle for power-constrained applications
using the conventional silicon complementary metal-oxide-semiconductor (CMOS) …
using the conventional silicon complementary metal-oxide-semiconductor (CMOS) …