Handwriting and signature: one or two personality identifiers?
Handwriting and signature are often studied without any connection, In this paper, we
present a method applied both to handwriting and signature classification that is based on …
present a method applied both to handwriting and signature classification that is based on …
A DSP acceleration framework for software-defined radios on x86 64
G Georgis, A Thanos, M Filo… - ICASSP 2020-2020 …, 2020 - ieeexplore.ieee.org
This paper presents a DSP acceleration and assessment framework targeting SDR
platforms on x86_64 architectures. Driven by the potential of rapid prototyping and …
platforms on x86_64 architectures. Driven by the potential of rapid prototyping and …
Performance-energy optimizations for shared vector accelerators in multicores
SF Beldianu, SG Ziavras - IEEE Transactions on Computers, 2014 - ieeexplore.ieee.org
For multicore processors with a private vector coprocessor (VP) per core, VP resources may
not be highly utilized due to limited data-level parallelism (DLP) in applications. Also, under …
not be highly utilized due to limited data-level parallelism (DLP) in applications. Also, under …
具有高效混洗模式存储器的可编程混洗单元
万江华， 刘胜， 周锋， 王耀华， 陈书明 - 国防科技大学学报, 2011 - journal.nudt.edu.cn
为向量DSP 提出并设计了一种具有高效混洗模式存储器的可编程混洗单元,
该结构能够使应用程序的混洗指令在执行时和通用寄存器或访存带宽等系统的关键资源分离 …
该结构能够使应用程序的混洗指令在执行时和通用寄存器或访存带宽等系统的关键资源分离 …
On the scalability of SIMD processing for software defined radio algorithms
P Westermann, H Schröder - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
Software defined radio (SDR) systems require programmable architectures that provide high
performance combined with high energy efficiency. Wide single instruction, multiple data …
performance combined with high energy efficiency. Wide single instruction, multiple data …
An Implementation of Configurable SIMD Core on FPGA
G Wang, YS Gao - Applied Mechanics and Materials, 2013 - Trans Tech Publ
In order to meet the computing speed required by 4G wireless communications, and to
provide the different data processing widths required by different algorithms, an SIMD …
provide the different data processing widths required by different algorithms, an SIMD …
Towards a High-performance and Reliable System for Emerging Edge Network
J Wang - 2022 - utd-ir.tdl.org
Abstract 5G is a new paradigm that enables tremendous opportunities by delivering high-
bandwidth and low-latency network. The emerging 5G-enhanced applications including …
bandwidth and low-latency network. The emerging 5G-enhanced applications including …
Supporting efficient Memory conflicts reduction using the DMA Cache technique in vector DSPs
S Liu, SM Chen, HY Chen, SG Chen… - 2011 IEEE Sixth …, 2011 - ieeexplore.ieee.org
This paper presents a Vector DMA Cache (VDC) scheme between the DMA bus and the
Vector Memory (VM) in vector DSPs. The VDC can effectively reduce the VM access counts …
Vector Memory (VM) in vector DSPs. The VDC can effectively reduce the VM access counts …
Modeling Scalable SIMD DSPs in LISA
P Westermann, H Schröder - … , SAMOS 2009, Samos, Greece, July 20-23 …, 2009 - Springer
Single instruction multiple data (SIMD) processing is an important technique for achieving
high performance in applications with innate data level parallelism such as applications from …
high performance in applications with innate data level parallelism such as applications from …
Review of Parallel Decoding of Space-Time Block Codes toward 4G Wireless and Mobile Communications
This paper presents a review of recent developments in the area of STBC decoding
particularly parallel decoding of full-rate full-diversity STBCs toward real-time 4G wireless …
particularly parallel decoding of full-rate full-diversity STBCs toward real-time 4G wireless …