LDMOS device with isolation guard rings

FH Chen, RH Liu - US Patent 6,924,531, 2005 - Google Patents
(57) ABSTRACT A method of forming a LDMOS semiconductor device and Structure for
Same. A preferred embodiment comprises form ing a first guard ring around and proximate …

Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication

SH Voldman - US Patent 7,541,247, 2009 - Google Patents
The present invention provides a semiconductor structure, comprising (a) a semiconductor
Substrate which includes a top substrate surface which defines a reference direction per …

[图书][B] ESD: design and synthesis

SH Voldman - 2011 - books.google.com
Electrostatic discharge (ESD) continues to impact semiconductor components and systems
as technologies scale from micro-to nano-electronics. This book studies electrical …

Integrated semiconductor device having isolation structure for reducing noise

HC Kim, HB An, IC Jung, JH Lee, KH Lee - US Patent 10,074,644, 2018 - Google Patents
An integrated semiconductor device includes a first transis tor and a second transistor
formed on a semiconductor substrate, and an isolation structure located adjacent to the …

Structure, structure and method of latch-up immunity for high and low voltage integrated circuits

SH Voldman - US Patent 8,519,402, 2013 - Google Patents
Design structures, structures and methods of manufacturing structures for providing latch-up
immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub …

Semiconductor device

K Watanabe - US Patent 6,921,959, 2005 - Google Patents
(57) ABSTRACT A Semiconductor device includes a Semiconductor Substrate, an insulating
layer, an inductor, a guard ring and a potential applying line. The insulating layer is formed …

Seal ring for mixed circuitry semiconductor devices

S Mallikarjunaswamy, M Alter - US Patent 7,145,211, 2006 - Google Patents
In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from
the Substrate and its electrical potential is provided in order to segregate noise sensitive …

Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication

SH Voldman - US Patent 8,110,853, 2012 - Google Patents
(57) ABSTRACT A semiconductor structure. The semiconductor structure includes a
semiconductor Substrate, a first transistor on the semiconductor Substrate, and a guard ring …

Compact guard ring structure for CMOS integrated circuits

S Mallikarjunaswamy - US Patent 9,373,682, 2016 - Google Patents
HO1L 29/7816 USPC........... 257/E21427, E23. 002, E29, 063, 126, 257/335, 336,618, 758;
327/109 See application file for complete search history. guard rings are formed in P-wells …

Protection device and related fabrication methods

R Zhan, CE Gill, WY Chen, MH Kaneshiro - US Patent 9,502,890, 2016 - Google Patents
BACKGROUND Modern electronic devices, and particularly, integrated circuits, are at risk of
damage due to electrostatic discharge (ESD) events. During an ESD event, a voltage (or …