Today's advanced high‐speed technology requires building behavioral models of systems,
from measured/simulated data, with increasingly higher operating frequencies. Different …

In this paper a block circuit elimination method is proposed for realizable reduction of
resistor-capacitor-inductor (RCL) networks. It is an extension of a recently published …

The TICER (TIme-Constant Equilibration Reduction) algorithm is a well-known resistor-
capacitor (RC) network reduction algorithm. It finds wide applications in integrated circuit …

SPICE (Simulation Program with Integrated Circuit Emphasis) is a widely used circuit
simulation framework for integrated circuit designs. The basic skeleton of SPICE time …

Model order reduction (MOR) techniques play a crucial role in the computer-aided design of
modern integrated circuits, where they are used to reduce the size of parasitic networks …

During the past decade, model order reduction (MOR) has become key enabler for the
efficient simulation of large circuit models. MOR techniques based on balanced truncation …

We propose an efficient algorithmic framework for time-domain circuit simulation using
exponential integrators. This work addresses several critical issues exposed by previous …

This work generalises the various ways in which a sparse matrix--vector (SpMV)
multiplication can be vectorised. It arrives at a novel data structure that generalises three …

Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As
process technologies scale down towards nanometer regimes, the fast and accurate timing …

The integration of more components into ICs due to the ever increasing technology scaling
has led to very large parasitic networks consisting of million of nodes, which have to be …