Design of efficient reversible logic-based binary and BCD adder circuits

H Thapliyal, N Ranganathan - ACM Journal on Emerging Technologies …, 2013 - dl.acm.org
Reversible logic is gaining significance in the context of emerging technologies such as
quantum computing since reversible circuits do not lose information during computation and …

Design of high speed BCD adder using CMOS technology

A Al Share, FN Zghoul, O Al-Khaleel… - IEEE …, 2023 - ieeexplore.ieee.org
Decimal arithmetic gains its importance in different applications in the fields of finance and
scientific applications. The approach of running decimal arithmetic over binary hardware …

Design of efficient BCD adders in quantum-dot cellular automata

G Cocorullo, P Corsonello, F Frustaci… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Among the emerging technologies recently proposed as alternatives to the classic CMOS,
quantum-dot cellular automata (QCA) is one of the most promising solutions to design …

A survey of hardware designs for decimal arithmetic

LK Wang, MA Erle, C Tsen… - IBM Journal of …, 2010 - ieeexplore.ieee.org
Decimal data and decimal arithmetic operations are ubiquitous in daily life. Although
microprocessors normally use binary arithmetic for computations, decimal arithmetic is often …

Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding

M Tosini, M Vázquez, L Leiva - The Journal of Supercomputing, 2024 - Springer
This paper proposes efficient implementations for addition/subtraction based on decimal
floating point with Densely Packed Decimal (DPD) and Binary Integer Decimal (BID) …

Low area/power decimal addition with carry-select correction and carry-select sum-digits

M Dorrigiv, G Jaberipur - Integration, 2014 - Elsevier
We improve a carry-select technique for decimal adders, where pairs of corrective carry-out
bits for all decimal positions are computed in parallel. Selection is based on the …

Modified reduced delay BCD adder

C Sundaresan, CVS Chaitanya… - 2011 4th …, 2011 - ieeexplore.ieee.org
Current trends in the academia and industry is managing and processing a high volume of
data. Most of the time is spend on converting the data from decimal to binary, processing …

An improved BCD adder using 6-LUT FPGAs

S Gao, D Al-Khalili, N Chabini - 10th IEEE International …, 2012 - ieeexplore.ieee.org
The need for high performance decimal arithmetic is required in many applications. Using
binary system to process decimal numbers tends to be costly in terms of area and speed …

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

H Neto, M Vestias - Microprocessors and Microsystems, 2017 - Elsevier
Decimal arithmetic has recovered the attention in the field of computer arithmetic due to
decimal precision requirements of application domains like financial, commercial and …

Implementation of low power BCD adder using gate diffusion input cell

G Saida, S Meena - 2016 International conference on …, 2016 - ieeexplore.ieee.org
Now-a-days reducing the power consumption of the device is the most important factor in
VLSI design. This paper deals with the low power, full voltage swing BCD addition using …