A statistical gate sizing method for timing yield and lifetime reliability optimization of integrated circuits

SM Ebrahimipour, B Ghavami… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
As CMOS devices become smaller, process and aging variations become a major issue for
circuit reliability and yield. In this paper, we propose a new two-phase gate sizing approach …

History of inheritance

D Ceccarelli - Encyclopedia of Evolutionary Psychological Science, 2021 - Springer
Much of the way we are shaped by evolution is indicative of the kind of environment we had
to survive in. Early records show that we, as humans, had to survive at one point in trees as …

Hot Carrier Degradation-Induced Variability in Different Lightly Doped Drain Processes: From Transistors to SRAM Cells

Q Teng, Y Wu, K Xu, D Gao - IEEE Transactions on Electron …, 2024 - ieeexplore.ieee.org
In this work, the impact of lightly doped drain (LDD) implantation doses on hot carrier
degradation (HCD) variability behaviors has been studied for transistors and static random …

Comparison of variability of HCI induced drift for SiON and HKMG devices

X Federspiel, C Diouf, F Cacho… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
We present here a detailed comparison of HCI induced drift of logic devices parameters from
40nm SiON and 28nm HKMG nodes. Repeated HCI stress with sampling ranging from 70 to …

Foldback Current Limiting in Low-Dropout Voltage Regulators with Aging Analysis Based Operating Envelope

H Sahakyan - 2023 IEEE East-West Design & Test Symposium …, 2023 - ieeexplore.ieee.org
A design methodology for aging aware foldback current limiting is presented. Traditional
constant and foldback limiting techniques are reviewed in the context of hot carrier induced …

On the Resiliency of Physically Unclonable Functions against Power Analysis Attacks

TAP Kroeger - 2022 - search.proquest.com
Abstract Integrated Circuits (ICs) have made their way into many critical systems that service
transportation, medical, and military industries; areas that are targeted for maximum …

Implementation-based design fingerprinting for robust IC fraud detection

J Shey, N Karimi, R Robucci, C Patel - Journal of Hardware and Systems …, 2019 - Springer
With the global spanning of integrated circuit (IC) and electronic device supply chains, the
ability of an untrusted foundry to alter a design for intellectual property (IP)/IC piracy …

Power Supply Analysis for Device Verification

J Shey - 2020 - search.proquest.com
With the global spanning of integrated circuit (IC) and electronic device supply chains, the
ability of an untrusted entity to alter an IC or device while it is in the supply chain increases …