STT-MRAM is a promising candidate to replace SRAM in Last Level Caches (LLCs) thanks
to its high density and reduced leakage. However, write delay, write energy, defects and risk …

This paper presents a physics-based compact model for Voltage-Controlled Magnetic
Anisotropy (VCMA) MRAM, calibrated against fabricated devices. Our model addresses …

We introduce a novel 1T1R bitcell design to address the challenges posed by the high
current requirement during the Parallel to Anti-Parallel (P2AP) transition in STT-MRAM. This …

A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-
MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE …

This paper introduces a comprehensive optimization framework designed to enhance the
regression of physical parameters for MRAM technologies, including STT-MRAM, VCMA …

Over the past decades, several emerging memory devices have been introduced with the
aim of enhancing circuit performance. Spin-transfer torque magnetic tunnel junction (STT …