[HTML][HTML] {VectorVisor}: A Binary Translation Scheme for {Throughput-Oriented}{GPU} Acceleration

S Ginzburg, M Shahrad, MJ Freedman, Z Wen… - 2023 USENIX Annual …, 2023 - usenix.org
Papers are available for download below to registered attendees now. The papers and the
full proceedings will be available to everyone beginning Monday, July 10, 2023. Paper …

EVMTracer: Dynamic Analysis of the Parallelization and Redundancy Potential in the Ethereum Virtual Machine

X Hu, B Burgstaller, B Scholz - IEEE Access, 2023 - ieeexplore.ieee.org
Ethereum is one of the first blockchains executing smart contracts, ie, financial applications
directly executed on the ledger using a virtual machine. High transaction volumes caused by …

Accelerating OCaml programs on FPGA

L Sylvestre, E Chailloux, J Sérot - International Journal of Parallel …, 2023 - Springer
This paper aims to exploit the massive parallelism of Field-Programmable Gate Arrays
(FPGAs) by programming them in OCaml, a multiparadigm and statically typed language. It …

[PDF][PDF] Towards higher-level synthesis and co-design with python

A Quenon, VRG da Silva - Proceedings of the Workshop …, 2021 - applications.umons.ac.be
Several methods have arisen to fasten the hardware design process. Among them, the high-
level synthesis (HLS), ie, the use of a higherlevel programming language than the usual …

Accelerating WebAssembly Interpreters in Embedded Systems Through Hardware-Assisted Dispatching

M Rupp, J Schröter, S Wallentowitz - International Conference on …, 2024 - Springer
WebAssembly is a promising bytecode virtualization technology for embedded systems.
WebAssembly interpreters for embedded demonstrate strong isolation and portability …

[PDF][PDF] Towards Higher-Level Synthesis and Co-design

A Quenon, VRG da Silva - 2021 - apps.umons.ac.be
Several methods have arisen to fasten the hardware design process. Among them, the high-
level synthesis (HLS), ie, the use of a higher-level programming language than the usual …