The challenges and emerging technologies for low-power artificial intelligence IoT systems
L Ye, Z Wang, Y Liu, P Chen, H Li… - … on Circuits and …, 2021 - ieeexplore.ieee.org
The Internet of Things (IoT) is an interface with the physical world that usually operates in
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning
The growing computational demand in artificial intelligence calls for hardware solutions that
are capable of in situ machine learning, where both training and inference are performed by …
are capable of in situ machine learning, where both training and inference are performed by …
Neuromorphic spiking neural networks and their memristor-CMOS hardware implementations
LA Camuñas-Mesa, B Linares-Barranco… - Materials, 2019 - mdpi.com
Inspired by biology, neuromorphic systems have been trying to emulate the human brain for
decades, taking advantage of its massive parallelism and sparse information coding …
decades, taking advantage of its massive parallelism and sparse information coding …
A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices
JM Hung, CX Xue, HY Kao, YH Huang, FC Chang… - Nature …, 2021 - nature.com
Non-volatile computing-in-memory (nvCIM) architecture can reduce the latency and energy
consumption of artificial intelligence computation by minimizing the movement of data …
consumption of artificial intelligence computation by minimizing the movement of data …
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu… - Nature …, 2021 - nature.com
The development of small, energy-efficient artificial intelligence edge devices is limited in
conventional computing architectures by the need to transfer data between the processor …
conventional computing architectures by the need to transfer data between the processor …
A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices
YC Chiu, WS Khwa, CS Yang, SH Teng, HY Huang… - Nature …, 2023 - nature.com
Artificial intelligence edge devices should offer high inference accuracy and rapid response
times, as well as being energy efficient. Ensuring the security of these devices against …
times, as well as being energy efficient. Ensuring the security of these devices against …
Microprocessor optimizations for the internet of things: A survey
The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely
identifiable physical devices. These devices' goal is to gather data and drive actions in order …
identifiable physical devices. These devices' goal is to gather data and drive actions in order …
AccuReD: High accuracy training of CNNs on ReRAM/GPU heterogeneous 3-D architecture
The growing popularity of convolutional neural networks (CNNs) along with their complexity
has led to the search for efficient computational platforms suitable for them. Resistive …
has led to the search for efficient computational platforms suitable for them. Resistive …
Enabling energy-efficient nonvolatile computing with negative capacitance FET
Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-
switching capability at a low voltage and the associated benefits for implementing energy …
switching capability at a low voltage and the associated benefits for implementing energy …
A 47.14- 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
The demand for energy-efficient, high-performance microcontroller units (MCUs) for the use
in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a …
in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a …