A short review of through-silicon via (TSV) interconnects: metrology and analysis

J Wang, F Duan, Z Lv, S Chen, X Yang, H Chen, J Liu - Applied Sciences, 2023 - mdpi.com
This review investigates the measurement methods employed to assess the geometry and
electrical properties of through-silicon vias (TSVs) and examines the reliability issues …

Comparison of mechanical modeling to warpage estimation of RDL-first fan-out panel-level packaging

CC Lee, CW Wang, CY Chen - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
To meet the requirements of low cost, thin vehicles, and multiple functions, the fan-out panel-
level packaging (FO-PLP) is introduced to be one of the next-generation packaging …

Research on equivalent modeling and model testing verification methods for material mechanics parameters of TXV structure

T Gu, N Liu, Z Feng, X Sun, X Meng - Microelectronics Reliability, 2024 - Elsevier
Aiming at the problems of multi-scale mesh division and low computational efficiency
encountered during TXV (through X via) structural simulation, an equivalent modeling …

3D printing/electrospinning of a bilayered composite patch with antibacterial and antiadhesive properties for repairing abdominal wall defects

Q Hu, Y Zhang, Y Song, H Shi, D Yang… - Journal of Materials …, 2024 - pubs.rsc.org
The application of patch methods for repairing abdominal wall wounds presents a variety of
challenges, such as adhesion and limited mobility due to inadequate mechanical strength …

Development of equivalent material properties of microbump for simulating chip stacking packaging

CC Lee, TL Tzeng, PC Huang - Materials, 2015 - mdpi.com
A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch
causes difficulty in analytic model construction. This paper proposes a simulation technique …

Warpage estimation of heterogeneous panel-level fan-out package with fine line RDL and extreme thin laminated substrate considering molding characteristics

CC Lee, CW Wang, CC Lee, CY Chen… - 2021 IEEE 71st …, 2021 - ieeexplore.ieee.org
To meet the requirements of achieving high density and heterogeneous integrations, fan-out
Panel level packaging (FOPLP) technology regarded as one of the promising alternative …

[HTML][HTML] Lifetime prediction of copper pillar bumps based on fatigue crack propagation

Y Zhou, Q Liu, T Ma, S Li, X Zhang - Frontiers in Materials, 2024 - frontiersin.org
2.5 D package realizes the interconnection of multiple dies through Si interposers, which
can greatly improve the data transmission rate between dies. However, its multi-layer …

Demonstration of an equivalent material approach for the strain-induced reliability estimation of stacked-chip packaging

CC Lee, PC Huang, YC Lin… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A huge shift in classical system integration composed of heterogeneous and homogeneous
substances from 2D to 2.5 D or even 3D assembly is a promising solution to satisfying the …

Polystyrene/TiO2 nanocomposite coating for strength and toughness enhancement of aluminum alloy 2024–T3 in accelerated stress corrosion cracking

CF Chen, BV Baart, J Zhang, L Zhang - Progress in Organic Coatings, 2021 - Elsevier
The polystyrene/TiO 2 nanocomposite coating is evaluated for reducing the susceptibility of
aluminum alloy AA2024-T3 to stress corrosion cracking (SCC). The as-synthesized titania …

Pcb embedded chip-on-chip packaging of a 48 kw sic mosfet dc-ac module with double-side cooling design

Y Yang, A Emadi - 2020 IEEE Transportation Electrification …, 2020 - ieeexplore.ieee.org
Packaging technology is a major challenge to tapping the performance potential of wide
bandgap devices. This paper proposes a packaging design based on the printed circuit …