A sub-1-V 8.5-ppm/° C sampled bandgap voltage reference

RK Palani, S Bhagavatula… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a
constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled …

A Novel Frequency Compensation Scheme for Heavy Load LDO with Improved Load Regulation and High Open Loop Gain

J Li, S Wang, T Zhao, X Yang, Z Xiao… - IEEJ Transactions on …, 2023 - Wiley Online Library
This paper presents a novel frequency compensation scheme for the stability of low dropout
regulator (LDO). The proposed compensation scheme introduces a zero in the voltage …

A three-stage OTA with hybrid active miller enhanced compensation technique for large to heavy load applications

S Dong, C Liu, X Xin, X Tong - Microelectronics Journal, 2021 - Elsevier
A three-stage amplifier with hybrid active Miller enhancement compensation is proposed in
this paper, which is used for large to heavy load applications. The hybrid active Miller …

A Capacitor-Free Low-Dropout Regulator with Low Line Regulation Rate and High Stability

Y Liang, S Diao - 2021 14th International Congress on Image …, 2021 - ieeexplore.ieee.org
A Capacitor-Free Low-Dropout Regulator (LDO) for power adapter with an input voltage
range of 8V∼ 24V is presented in this paper. The proposed LDO structure uses a high …

High audio band PSR and fast settling-time dual-loop LDO regulator architecture for low-power application

E Barteselli, L Sant, R Gaggl… - … Conference on Electrical …, 2021 - ieeexplore.ieee.org
This paper presents a fully integrated 65nm CMOS Low-Dropout (LDO) voltage regulator for
MEMS devices in the microphone field. The proposed LDO exploits a nested loop to …

基于负载跟踪技术的低漏失大电流LDO 的设计.

茅欣彧, 汪西虎, 姚和平… - Electronic Components & …, 2022 - search.ebscohost.com
为了满足便携式电子设备的需求, 设计了一种低漏失高稳定的LDO. 利用正反馈环路钳位电压,
获得高精度采样电流. 通过调整工作在深线性区的MOS 管的等效电阻, 产生跟踪负载电流的零点 …

A 0.6–1.8 V/0.4–1.6 V input/output LDO with high PSRR over 50 dB/30 dB in dual-modes

S Dong, S Bu, X Tong - Circuits, Systems, and Signal Processing, 2023 - Springer
A output-capacitorless, wide range 0.6–1.8 V/0.4–1.6 V input/output, dual-mode low-dropout
regulator with a high-power supply rejection ratio (PSRR) is proposed in this paper. When …

High power low cross-talk single inductor dual output DC-DC converter for power management in PLL IC

S Zhong, Z Chen, B Li, R Wang, X Wu… - Journal of Physics …, 2024 - iopscience.iop.org
A single inductor dual output DC-DC converter operating in CCM mode is proposed in this
paper. Due to the more accuracy and complete small-signal model in Simulink and the …

Low power consumption and fast response of low dropout regulator design

T Wei, S Huang, S Wang - Journal of Physics: Conference Series, 2024 - iopscience.iop.org
A low power consumption and fast response low voltage difference linear regulator circuit is
designed for on-chip SOC circuit to achieve low power consumption, fast response, and high …

An LDO without a Capacitor Required in Applications

L Shi, J Fan, S Huang - Journal of Physics: Conference Series, 2023 - iopscience.iop.org
Linear voltage regulator with low voltage dropout is widely used in DC/DC circuits because
of the advantages of simple structure, low noise, high efficiency, and small package size. In …