Soft-OLP: Improving hardware cache performance through software-controlled object-level partitioning
Performance degradation of memory-intensive programs caused by the LRU policy's
inability to handle weak-locality data accesses in the last level cache is increasingly serious …
inability to handle weak-locality data accesses in the last level cache is increasingly serious …
Set associative cache memory with heterogeneous replacement policy
RE Hooker, DR Reed, JM Greer, C Eddy - US Patent 9,811,468, 2017 - Google Patents
(57) ABSTRACT A set associative cache memory, comprising: an array of storage elements
arranged as M sets by N ways; an alloca tion unit that allocates the storage elements in …
arranged as M sets by N ways; an alloca tion unit that allocates the storage elements in …
A novel asynchronous software cache implementation for the cell-be processor
This paper describes the implementation of a runtime library for asynchronous
communication in the Cell BE processor. The runtime library implementation provides with …
communication in the Cell BE processor. The runtime library implementation provides with …
Buffer-Integrated-Cache: A cost-effective SRAM architecture for handheld and embedded platforms
In an SoC, building local storage in each accelerator is area inefficient due to the low
average utilization. In this paper, we present design and implementation of Buffer-integrated …
average utilization. In this paper, we present design and implementation of Buffer-integrated …
MetaSys: A practical open-source metadata management system to implement and evaluate cross-layer optimizations
This article introduces the first open-source FPGA-based infrastructure, MetaSys, with a
prototype in a RISC-V system, to enable the rapid implementation and evaluation of a wide …
prototype in a RISC-V system, to enable the rapid implementation and evaluation of a wide …
Cache memory budgeted by ways based on memory access type
RE Hooker, DR Reed, JM Greer, C Eddy - US Patent 9,910,785, 2018 - Google Patents
A set associative cache memory, comprising: an array of storage elements arranged as N
ways; an allocation unit that allocates the storage elements of the array in response to …
ways; an allocation unit that allocates the storage elements of the array in response to …
Cache memory budgeted by chunks based on memory access type
RE Hooker, DR Reed, JM Greer, C Eddy - US Patent 9,898,411, 2018 - Google Patents
A set associative cache memory, comprising: an array of storage elements arranged as M
sets by N ways, each set belongs in one of L mutually exclusive groups; an allocation unit …
sets by N ways, each set belongs in one of L mutually exclusive groups; an allocation unit …
SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems
Although multi-core processors enhance the performance yet the challenge of estimating
Worst-Case Execution Time (WCET) of a task remains in such systems due to interference in …
Worst-Case Execution Time (WCET) of a task remains in such systems due to interference in …
Com-CAS: Effective Cache Apportioning under Compiler Guidance
With a growing number of cores in modern high-performance servers, effective sharing of
the last level cache (LLC) is more critical than ever. The primary agenda of such systems is …
the last level cache (LLC) is more critical than ever. The primary agenda of such systems is …
Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
DR Reed - US Patent 9,798,668, 2017 - Google Patents
A cache memory stores 2^ J-byte cache lines and includes an array of 2^ N sets each
holding tags each X bits, an input receives a Q-bit memory address, MA [(Q− 1): 0], having: a …
holding tags each X bits, an input receives a Q-bit memory address, MA [(Q− 1): 0], having: a …