Multiplying delay-locked loop using sampling time-to-digital converter
H Wang, O Burg - US Patent 10,250,264, 2019 - Google Patents
(Continued) Primary Examiner—Lincoln D Donovan Assistant Examiner—Khareem E Almo
(57) ABSTRACT A multiplying delay-locked loop circuit includes a delay chain including a …
(57) ABSTRACT A multiplying delay-locked loop circuit includes a delay chain including a …
Subsampling motion detector for detecting motion of object under measurement
TP Chen - US Patent 10,411,716, 2019 - Google Patents
A subsampling motion detector configured to detect motion information of an object under
measurement receives a first wireless radio frequency (RF) signal and transmits a second …
measurement receives a first wireless radio frequency (RF) signal and transmits a second …
Injection-locked digital bang-bang phase-locked loop with timing calibration
TK Kuan, CY Wu, RB Sheen, CH Chang - US Patent 10,374,617, 2019 - Google Patents
A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-
locked loop (PLL) electrically connected to an input clock signal connection and an output …
locked loop (PLL) electrically connected to an input clock signal connection and an output …
Phase-locked loop circuit and clock generator including the same
A phase-locked loop (PLL) circuit may include a voltage controlled oscillator, a sub-
sampling PLL circuit, and a fractional frequency division control circuit. The fractional …
sampling PLL circuit, and a fractional frequency division control circuit. The fractional …
Method and apparatus for generating clock
SJ Kim, JW Lee, JO Min-Gyu… - US Patent 10,693,472, 2020 - Google Patents
A clock generation apparatus includes a pulse generator configured to generate a pulse
signal and a selection signal using a reference clock signal, a delay line circuit, a switch and …
signal and a selection signal using a reference clock signal, a delay line circuit, a switch and …
Systems and methods for ultra wideband impulse radio transmitters
H04L 7700(2006.01) H04B 1/16(2006.01) H04B 13827(2015.01) H04L 25/49(2006.01)
H04L 27/22(2006.01) H04L 1/00(2006.01) H04L 27/26(2006.01) H04L 5/00(2006.01) H04B …
H04L 27/22(2006.01) H04L 1/00(2006.01) H04L 27/26(2006.01) H04L 5/00(2006.01) H04B …
Digital phase locked loop and methods of operating same
Y Lee, J Park, M Park, J Jinook, J Choi - US Patent 12,063,044, 2024 - Google Patents
A digital phase-locked loop (PLL) includes:(i) a digitally controlled oscillator (DCO)
configured to generate an oscillation signal having a frequency that is adjustable in …
configured to generate an oscillation signal having a frequency that is adjustable in …
Systems and methods for ultra wideband impulse radio protocols
Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide
frequency spectrum with very low power over a short distance for digital data transmission …
frequency spectrum with very low power over a short distance for digital data transmission …
Systems and methods for ultra wideband impulse radio transceivers
Related US Application Data continuation of application No. 16/261,797, filed on Jan. 30,
2019, now Pat. No. 11.201, 638, which is a continuation of application No. 15/578,478, filed …
2019, now Pat. No. 11.201, 638, which is a continuation of application No. 15/578,478, filed …
Systems and methods for ultra wideband impulse radio transceivers
2022-12-28 Assigned to TRANSFERT PLUS SOCIETE EN COMMANDITE reassignment
TRANSFERT PLUS SOCIETE EN COMMANDITE NUNC PRO TUNC ASSIGNMENT (SEE …
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