We survey recent developments in high level synthesis technology for VLSI design. The
need for higher-level design automation tools are discussed first. We then describe some …

We present a technique for deriving predictions for the run times of parallel applications from
the run times of “similar” applications that have executed in the past. The novel aspect of our …

Rapid advances in microelectronic integration and the advent of Systems-on-Chip have
fueled the need for high-level synthesis, ie, an automated approach to the synthesis of …

We present a high-level synthesis methodology that applies a coordinated set of coarse-
grain and fine-grain parallelizing transformations. The transformations are applied both …

As hardware designs get increasingly complex and time-to-market constraints get tighter
there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both …

The quality of synthesis results for most high-level synthesis approaches is strongly affected
by the choice of control flow (through conditions and loops) in the input description. This …

In this paper, we present a novel scheduling algorithm targeted toward minimizing the
average execution time of control-flow intensive behavioral descriptions. Our algorithm uses …

In this paper, we present a comprehensive high-level synthesis system that is geared toward
reducing power consumption in control-flow intensive as well as data-dominated circuits. An …

This paper presents a new methodology based on evolutionary multi-objective optimization
(EMO) to synthesize multiple complex modules on reprogrammable devices. It starts from a …

The desire for more mobility and the enthusiasm for ubiquitous electronic gadgets on the
one hand side and the steady progress in semiconductor industry on the other hand are the …