Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiers

VSM Srinivasavarma, SR Pydi… - The Journal of …, 2022 - Springer
Network intrusion detection systems (NIDS) require all the header matching rules to be
reported which is termed as multi-match packet classification. Ternary content-addressable …

Using FPGA-based content-addressable memory for mnemonics instruction searching in assembler design

H Öztekin, A Lazzem, İ Pehlivan - The Journal of Supercomputing, 2023 - Springer
Memories play an essential role in computer systems as they store and retrieve data that
may include instructions required for system operation. In the case of an assembler, the …

[HTML][HTML] A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

N Trinh, M Bui, B Dang, L Tran - Ain Shams Engineering Journal, 2024 - Elsevier
Abstract Ternary Content-Addressable Memory (TCAM) is one of the most effective methods
for high-speed data searching in networking infrastructure. Despite the excellent …

DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

S Vakili, A Zarei - IEEE Embedded Systems Letters, 2023 - ieeexplore.ieee.org
This letter introduces an original and highly efficient method to implement high-capacity
content-addressable memories on field programmable gate arrays (FPGAs). The method …

A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching

P Soleimani, DW Capson, KF Li - ACM Transactions on Reconfigurable …, 2024 - dl.acm.org
An efficient architecture for image descriptor matching that uses a partitioned content-
addressable memory (CAM)-based approach is proposed. CAM is frequently used in high …

A Reduced Hardware SNG for Stochastic Computing

C López-Magaña, J Rivera, S Ortega-Cisneros… - Electronics, 2023 - mdpi.com
Stochastic Computing (SC) is an alternative way of computing with binary weighted words
that can significantly reduce hardware resources. This technique relies on transforming …

TeRa: Ternary and Range based packet classification engine

M Dhayalakumar, NM Sk - Integration, 2024 - Elsevier
This work proposes a novel approach to the hardware implementation of packet
classification in ASICs, using NAND-NOR logic at each stage. The proposed design utilizes …

Implementation of LFSR based Fast Error-Resilient Ternary Content-Addressable Memory

G Karunakar, B Papachary - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
Memories are the major building blocks for various applications, which includes integrated
circuits, digital circuits, digital equipment. The conventional memories are developed using …

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

H Öztekin, İ Pehlivan, A Lazzem - Mühendislik Bilimleri ve …, 2023 - dergipark.org.tr
his work gives a comparison between two approaches used for improving search operation
speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a …

Accelerating DNA Sequence Analysis using content-addressable memory in FPGAs

M Irfan, K Vipin, R Qureshi - 2023 IEEE 8th International …, 2023 - ieeexplore.ieee.org
Biological sequence alignment is a widely used technique where the sequence databases
are searched to find similar sequence to the input query. In this work we focus on the most …