Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire

Y Wang, H Yu, D Sylvester… - 2014 Design, Automation & …, 2014 - ieeexplore.ieee.org
The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in
secure big-data storage. Data oriented applications have imposed high throughput and low …

[图书][B] Memristor device modeling and circuit design for read out integrated circuits, memory architectures, and neuromorphic systems

C Yakopcic - 2014 - search.proquest.com
Significant interest has been placed on developing systems based on the memristor, which
was physically recognized in 2008. The memristor is a nanoscale non-volatile device with a …

An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices

Y Wang, H Yu - … Symposium on Low Power Electronics and …, 2013 - ieeexplore.ieee.org
As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or
race-track) has shown potential for main memory storage but also computing capability. In …

Nonvolatile CBRAM-crossbar-based 3-D-integrated hybrid memory for data retention

Y Wang, H Yu, W Zhang - … on Very Large Scale Integration (VLSI …, 2013 - ieeexplore.ieee.org
This paper explores the design of 3-D-integrated hybrid memory by conductive-bridge
random-access-memory (CBRAM). Considering internal states, height, and radius of the …

[图书][B] Design exploration of emerging nano-scale non-volatile memory

H Yu, Y Wang - 2014 - Springer
The analysis of big data at exascale (1018 bytes or flops) has introduced the emerging need
to reexamine the existing hardware platform that can support intensive dataoriented …

Runtime thermal management for 3-D chip-multiprocessors with hybrid SRAM/MRAM L2 cache

S Lee, K Kang, CM Kyung - IEEE Transactions on Very Large …, 2014 - ieeexplore.ieee.org
Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low
leakage power while suffering from long write latency and high write energy, compared with …

Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures

M Gholipour, N Masoumi - Microelectronics Journal, 2013 - Elsevier
Nanowire crossbar is an efficient nanoscale architecture which can be used for logic circuit
design. In this work, we study and compare different crossbar nanoarchitectures and their …

HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis

S Seyedfaraji, M Bichl, A Aftab, S Rehman - IEEE Access, 2024 - ieeexplore.ieee.org
Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging Non-Volatile
Memory (NVM) technology that has garnered attention to overcome the drawbacks of …

A novel high performance and energy efficient NUCA architecture for STT-MRAM LLCs with thermal consideration

B Wu, P Dai, Y Cheng, Y Wang, J Yang… - … on Computer-Aided …, 2019 - ieeexplore.ieee.org
As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip
cache capacity increases to sustain the performance scaling. As a result, the cache power …

Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar

Y Wang, X Li, H Yu, L Ni, W Yang… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
The emerging resistive random-access-memory (RRAM) crossbar provides an intrinsic
fabric for matrix-vector multiplication, which can be leveraged as power efficient linear …