Spin-transfer torque magnetic memory (STT-MRAM) has gained significant research interest
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …

With increasing core-count, the cache demand of modern processors has also increased.
However, due to strict area/power budgets and presence of poor data-locality workloads …

In modern multi-processor systems-on-chip (MPSoCs), requests from different processor
cores, accelerators, and their responses from the lower-level memory contend for the shared …

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to
the critical loads from last level cache (LLC), which are frequently repeated, has become a …

Processing-in-Memory (PIM) has been proposed as a solution to accelerate data-intensive
applications, such as real-time Big Data processing and neural networks. The acceleration …

Non-volatile memories (NVMs) with their high storage density and ultra-low leakage power
offer promising potential for redesigning the memory hierarchy in next-generation Multi …

In a modern GPU architecture, all threads within a warp execute the same instruction in
lockstep. For a memory instruction, this can lead to memory divergence: the memory …

Contemporary multiprocessor systems-on-chips (MPSoCs) continue to confront energy-
related challenges, primarily originating from off-chip data movements. Nonvolatile …

The continued growth of the computational capability of throughput processors has made
throughput processors the platform of choice for a wide variety of high performance …

The rise of data-driven applications requires larger on-chip Last Level Caches (LLCs) in
multicore systems which need denser chips with lower power consumption. Non-Volatile …