FastSim: A fast simulation framework for high-level synthesis
M Abderehman, J Patidar, J Oza… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
High-level synthesis (HLS) is a well-established framework used to translate high-level
algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major …
algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major …
DEEQ: Data-driven end-to-end EQuivalence checking of high-level synthesis
M Abderehman, TR Reddy… - 2022 23rd International …, 2022 - ieeexplore.ieee.org
High-level synthesis (HLS) is widely used to translate a behavioural specification written in
C/C++ into a register transfer level (RTL) design. Due to the abstraction gap, it is a …
C/C++ into a register transfer level (RTL) design. Due to the abstraction gap, it is a …
Equivalence checking between SLM and RTL using machine learning techniques
J Hu, T Li, S Li - 2016 17th International Symposium on Quality …, 2016 - ieeexplore.ieee.org
The growing complexity of modern digital design makes designers shift toward starting
design exploration using high-level languages, and generating register transfer level (RTL) …
design exploration using high-level languages, and generating register transfer level (RTL) …
Scalable certification framework for behavioral synthesis front-end
Behavioral synthesis entails application of a sequence of transformations to compile a high-
level description of a hardware design (eg, in C/C++/SystemC) into a register-transfer level …
level description of a hardware design (eg, in C/C++/SystemC) into a register-transfer level …
Equivalence checking for compiler transformations in behavioral synthesis
Behavioral synthesis entails application of a sequence of transformations to compile a high-
level description of a hardware design (eg, in C/C++/SystemC) into a Register-Transfer …
level description of a hardware design (eg, in C/C++/SystemC) into a Register-Transfer …
A path-based equivalence checking method between system level and RTL descriptions using machine learning
J Hu, Y Hu, Q Lv, W Wang, G Wang… - Journal of Circuits …, 2021 - World Scientific
The growing complexity of modern digital design makes designers shift toward starting
design exploration using high-level languages, and generating register transfer level (RTL) …
design exploration using high-level languages, and generating register transfer level (RTL) …
Kairos: Incremental verification in high-level synthesis through latency-insensitive design
L Piccolboni, G Di Guglielmo… - 2019 Formal Methods in …, 2019 - ieeexplore.ieee.org
High-level synthesis (HLS) improves design productivity by replacing cycle-accurate
specifications with untimed or transaction-based specifications. Obtaining high-quality RTL …
specifications with untimed or transaction-based specifications. Obtaining high-quality RTL …
Formally analyzing fault tolerance in datapath designs using equivalence checking
In this paper, we present an efficient formal approach to check the equivalence of
synthesized Register Transfer Level (RTL) against the high level specification in the …
synthesized Register Transfer Level (RTL) against the high level specification in the …
[图书][B] Multi-Functional Interfaces for Accelerators
L Piccolboni - 2022 - search.proquest.com
Abstract Heterogeneous System-on-Chip (SoC) architectures combine general-purpose
processors with many accelerators, which are application-specific computing engines. By …
processors with many accelerators, which are application-specific computing engines. By …
[PDF][PDF] SoC 高级综合验证研究进展
胡健， 胡永扬， 王观武， 陈桂林， 杨海涛， 康云… - 计算机辅助设计与图形学 …, 2021 - jcad.cn
针对近年来片上系统(system on chip, SoC) 高级综合验证领域的工作, 首先分析了高级综合验证
的难点, 然后根据应用领域将算法分为3 类: 高级综合前端验证算法, 高级综合调度验证算法和 …
的难点, 然后根据应用领域将算法分为3 类: 高级综合前端验证算法, 高级综合调度验证算法和 …