Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution for independent ageing: The RADIO perspective

C Antonopoulos, G Keramidas, NS Voros… - … Symposium, ARC 2015 …, 2015 - Springer
Demographic and epidemiologic transitions in Europe have brought a new health care
paradigm where life expectancy is increasing as well as the need for long-term care. To …

A Defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems

M Mavropoulos, G Keramidas… - … Design, Automation & …, 2015 - ieeexplore.ieee.org
As process technology continues to shrink, a large number of bitcells in on-chip caches is
expected to be faulty. The number of defective cells varies from die-to-die, wafer-to-wafer …

Enabling efficient sub-block disabled caches using coarse grain spatial predictions

M Mavropoulos, G Keramidas, D Nikolos - Microprocessors and …, 2022 - Elsevier
Reducing the supply voltage in today′ s process technologies introduces significant
reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance …

A fault-tolerant last level cache for CMPs operating at ultra-low voltage

A Ferrerón, J Alastruey-Benedé, DS Gracia… - Journal of Parallel and …, 2019 - Elsevier
Voltage scaling to values near the threshold voltage is a promising technique to hold off the
many-core power wall. However, as voltage decreases, some SRAM cells are unable to …

Recovery of performance degradation in defective branch target buffers

F Filippou, G Keramidas… - 2016 IEEE 22nd …, 2016 - ieeexplore.ieee.org
Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management
technique. Unfortunately, voltage scaling increases the impact of process variations on …

ReMiT: Redundancy migration for latency aware fault tolerant cache design in multicore

A Choudhury, B Mondal… - 2018 8th International …, 2018 - ieeexplore.ieee.org
Power dissipation in Chip Multiprocessors (CMPs) has been addressed by Dynamic Voltage
and Frequency Scaling (DVFS). But uncontrolled reduction of voltage supply results in …

CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance

A Choudhury, BK Sikdar - 2017 7th International Symposium …, 2017 - ieeexplore.ieee.org
Dynamic voltage and frequency scaling puts threats to reliability in Chip Multiprocessors
(CMPs). Cache being the most susceptible to faults, the fault tolerance techniques are …

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems

M Mavropoulos, G Keramidas… - Proceedings of the 25th …, 2015 - dl.acm.org
Processor caches play a critical role in the performance of today" s computer systems. As
technology scales, due to manufacturing defects and process variations a large number of …

A novel fault tolerant cache architecture based on orthogonal latin squares theory

F Filippou, G Keramidas… - … Design, Automation & …, 2018 - ieeexplore.ieee.org
Aggressive dynamic voltage and frequency scaling is widely used to reduce the power
consumption of microprocessors. Unfortunately, voltage scaling increases the impact of …

Performance Degrading Faults in Branch Target Buffers and Branch Predictors: Exploration and Remedy

F Filippou, G Keramidas, M Mavropoulos… - Available at SSRN … - papers.ssrn.com
Voltage scaling increases the impact of process variations resulting in an exponential ramp-
up in the number of malfunctioning SRAM cells. Our experimental findings reveal that for …