This work revisits the design of crossbar and high-radix interconnects in light of advances in
circuit and layout techniques that improve crossbar scalability, obviating the need for deep …

This article examines the technological capabilities that national organizations generated
and accumulated throughout the long-term evolution of the miniaturization trajectory, the …

We describe the design and layout of a radix-128 crossbar in 90 nm CMOS. The data path is
32 bits wide and runs at 750 MHz using a three-stage pipeline, while fitting in a silicon area …

In this paper, we explore the challenges in scaling on-chip networks towards kilo-core
processors. Current low-radix topologies optimize for fast local communication, but do not …

Neural scene representation (NSR) initiates a new methodology of encoding a 3D scene
with neural networks by learning from dozens of photos taken from different camera …

In single-chip parallel processors, it is crucial to implement a high-throughput low-latency
interconnection network to connect the on-chip components, especially the processing units …

We describe the implementation of a 128× 128 crossbar switch in 90 nm CMOS standard-
cell ASIC technology. The crossbar operates at 750 MHz and is 32-bits for a port capacity …

We present a new type of soft‐core processor called the “Data‐Flow Soft‐Core” that can be
implemented through FPGA technology with adequate interconnect resources. This …

The increasing core count in manycore systems requires a corresponding large Network-on-
chip (NoC) bandwidth to support the overlying applications. However, it is not possible to …

On-chip shared cache is effective to alleviate the memory bottleneck in modern many-core
systems, such as GPGPUs. However, when scheduling numerous concurrent threads on a …