[HTML][HTML] Evaluating single event upsets in deep neural networks for semantic segmentation: An embedded system perspective
J Gutiérrez-Zaballa, K Basterretxea… - Journal of Systems …, 2024 - Elsevier
As the deployment of artificial intelligence (AI) algorithms at edge devices becomes
increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based …
increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based …
BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators
Compute-in-memory based binary neural networks or CiM-BNNs offer high energy/area
efficiency for the design of edge deep neural network (DNN) accelerators, with only a mild …
efficiency for the design of edge deep neural network (DNN) accelerators, with only a mild …
Tfix: Exploiting the natural redundancy of ternary neural networks for fault tolerant in-memory vector matrix multiplication
In-memory computing (IMC) and quantization have emerged as promising techniques for
edge-based deep neural network (DNN) accelerators by reducing their energy, latency and …
edge-based deep neural network (DNN) accelerators by reducing their energy, latency and …
SoK: Model Reverse Engineering Threats for Neural Network Hardware
S Potluri, F Koushanfar - Cryptology ePrint Archive, 2024 - eprint.iacr.org
There has been significant progress over the past seven years in model reverse engineering
(RE) for neural network (NN) hardware. Although there has been systematization of …
(RE) for neural network (NN) hardware. Although there has been systematization of …
[HTML][HTML] Enabling Neuromorphic Computing for Artificial Intelligence with Hardware-Software Co-Design
In the last decade, neuromorphic computing was rebirthed with the emergence of novel
nano-devices and hardware-software co-design approaches. With the fast advancement in …
nano-devices and hardware-software co-design approaches. With the fast advancement in …