Optimization of GPU and CPU acceleration for neural networks layers implemented in python

R Dogaru, I Dogaru - 2017 5th International Symposium on …, 2017 - ieeexplore.ieee.org
Many neural architectures including RBF, SVM, FSVC classifiers, or deep-learning solutions
require the efficient implementation of neurons layers, each of them having a given number …

Evaluation of DarkNet19 and DarkNet53 Inference Time on CPU, GPU, and FPGA

GV Popescu, M Antonescu, AM Enescu… - 2024 IEEE 18th …, 2024 - ieeexplore.ieee.org
The Convolutional Neural Networks used in machine learning applications such as
handwriting recognition, object detection, or speech recognition are dealing with large …

Open-Source, Modular, Graphical FPGA Board-Level Simulator

GV Popescu, R Hobincu - 2022 14th International Conference …, 2022 - ieeexplore.ieee.org
This paper presents a software FPGA board simulator having Xilinx's Vivado toolchain as a
backend. It offers a GUI interface to basic components such as LEDs, buttons, and switches …

Compiling efficiently with arithmetic emulation for the custom-width connex vector processor

AE Şuşu - Proceedings of the 5th Workshop on Programming …, 2019 - dl.acm.org
Compiling from sequential C programs using LLVM for the wide Connex vector accelerator,
a competitive customizable architecture for embedded applications with 32 to 4096 16-bit …

[PDF][PDF] A Recursive Hierarchy for Accelerator-Level Parallelism

M Malița, GM Ștefan - avestia.com
The emergence, under the pressure of the ASICs imposed by the corporate space, of the
field of Accelerator-Level Parallelism (ALP) requires a theoretical analysis to avoid the …

[HTML][HTML] The Connex Project

M Antonescu, GV Popescu, V Serbu - users.dcae.pub.ro
The concept of Connex Memory (CM) is a sequel of the Lisp Machine project (see the story
in [Stefan'02]). The concept is first presented in [Stefan'85/91], but unpublished until 1991 …