A survey on deep learning hardware accelerators for heterogeneous hpc platforms

C Silvano, D Ielmini, F Ferrandi, L Fiorin… - arXiv preprint arXiv …, 2023 - arxiv.org
Recent trends in deep learning (DL) imposed hardware accelerators as the most viable
solution for several classes of high-performance computing (HPC) applications such as …

Emerging trends and obstacles in Damascus processing and electroplating for Chiplet industries: A review

Y Sun, Q Qiu, S Zhang, G Sun, W Yu, L Cao… - Materials Science in …, 2025 - Elsevier
The Chiplet is widely regarded as the most viable continuation of Moore's Law in the
“Beyond Moore” era. This is primarily due to its capability to circumvent complex process …

An Electrical–Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems

X Ma, Q Xu, C Wang, H Cao, J Liu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Chiplet heterogeneous integration (CHI) is one of the important technology choices to
continue Moore's law. However, due to the characteristics of high power and low supply …

Research progress of hybrid bonding technology for three-dimensional integration

A Zhou, Y Zhang, F Ding, Z Lian, R Jin, Y Yang… - Microelectronics …, 2024 - Elsevier
Computing power based artificial intelligence will profoundly change the productivity and
production relations, and the integrated circuit industry begin to rely on three-dimensional …

Deep Neural Network Accelerator: Exploring the Potential of 3D Chiplet Integration

S Wang, T Wang, S Bi, F Jiao… - 2024 7th International …, 2024 - ieeexplore.ieee.org
The development of deep neuro networks brings a sharp rise in demands for expeditious
convolutional computing operations, but the “memory wall” originated from the intense data …

The Energy-Efficient 10-Chiplet AI Hyperscale NPU on Large-Scale Advanced Package

J Yoon, Y Kwon, H Kim, J Lee, J Kim… - 2024 IEEE 74th …, 2024 - ieeexplore.ieee.org
In this paper, we presented an AI hyperscale processing unit (HPU), integrating a pair of
neural processing unit (NPU) and 8 high bandwidth memory (HBM) chiplets above a large …

ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing

Y Kwon - 2023 20th International SoC Design Conference …, 2023 - ieeexplore.ieee.org
Recent advancement of Large Language Model necessitates high-performance AI
processors with specialized architecture for Hyperscale Neural Network. A large amount of …

Effects of 2.5 D/3D Stacking Structure on Signal Integrity of Chiplet Interconnection

H Mao, H Xu, S Zhang, Y Dai, Z Cai… - 2024 25th International …, 2024 - ieeexplore.ieee.org
In the post-Moore era, the chiplet technology based on advanced packaging would be a
quite promising solution for the high-performance AI chips. The chiplet technology with 2.5 …