Heterogeneous reconfigurable systems provide drastically higher performance and lower
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …

The rapid increase of complexity in System-on-a-Chip design urges the design community to
raise the level of abstraction beyond RTL. Automated behavior-level and system-level …

Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the
regularity in applications for design optimizations. In this paper we present a general pattern …

With the rapid increase of complexity in system-on-a-chip (SoC) design, the electronic
design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis …

This paper describes a register and functional unit (FU) binding al-gorithm in high level
synthesis. Our algorithm targets the reduction of multiplexer inputs. Since multiplexers …

High-level synthesis (HLS) currently seems to be an interesting process to reduce the
design time substantially. HLS tools actually map algorithms to architectures. While such …

In a behavioral synthesis system, a typical approach used to guide the scheduler is to
impose hard constraints on the relative timing between operations considering performance …

Behavior synthesis and optimization beyond the register-transfer level require an efficient
utilization of the underlying platform features. This article presents a platform-based …

There are two prominent problems with technology scaling: increasing design complexity
and more challenges with interconnect design, including routability. High-level synthesis …

The rate of increase in computing performance has been slowing due to the end of
processor frequency scaling and diminishing returns from multiple cores. We believe the …