Shielding methodologies in the presence of power/ground noise
Design guidelines for shielding in the presence of power/ground (P/G) noise are presented
in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line …
in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line …
Evaluation and reduction of signal integrity issues in multiwalled carbon nanotube on-chip VLSI interconnects
Due to advancements in device scaling in very-large-scale integration (VLSI) technology,
signal integrity (SI) issues play a major role to determining the performance of on-chip …
signal integrity (SI) issues play a major role to determining the performance of on-chip …
VLSI interconnects and their testing: prospects and challenges ahead
Purpose–The purpose of this paper is to explore the functioning of very‐large‐scale
integration (VLSI) interconnects and modeling of interconnects and evaluate different …
integration (VLSI) interconnects and modeling of interconnects and evaluate different …
Interconnect noise analysis and optimization in deep submicron technology
MA Elgamel, MA Bayoumi - IEEE Circuits and Systems …, 2003 - ieeexplore.ieee.org
The migration to using ultra deep submicron (UDSM) process, 0.25 μm or below,
necessitates new design methodologies and EDA tools to address the new design …
necessitates new design methodologies and EDA tools to address the new design …
Post-route gate sizing for crosstalk noise reduction
Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route
design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for …
design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for …
Modeling single event crosstalk in nanometer technologies
S Sayil, VK Boorla, SR Yeddula - IEEE Transactions on Nuclear …, 2011 - ieeexplore.ieee.org
With advances in CMOS technology, circuits become increasingly more sensitive to transient
pulses caused by single event (SE) particles. On the other hand, coupling effects among …
pulses caused by single event (SE) particles. On the other hand, coupling effects among …
[图书][B] Compact models and performance investigations for subthreshold interconnects
Modern very-large-scale integration (VLSI) chips contain millions of transistors. It is
envisaged that VLSI chips will contain more than three billion transistors in the coming …
envisaged that VLSI chips will contain more than three billion transistors in the coming …
[PDF][PDF] Noise reduction in VLSI circuits using modified GA based graph coloring
T Maitra, AJ Pal, D Bhattacharyya… - International Journal of …, 2010 - researchgate.net
Analyzing and evaluating various noise avoidance techniques such as driver sizing, wire
sizing, wire spacing and layer assignment. This paper presents an approach to solve the …
sizing, wire spacing and layer assignment. This paper presents an approach to solve the …
Early probabilistic noise estimation for capacitively coupled interconnects
One of the critical challenges in today's high performance IC design is to take noise into
account as early as possible in the design cycle. Current noise analysis tools [1, 7} are …
account as early as possible in the design cycle. Current noise analysis tools [1, 7} are …
Using binary-reflected gray coding for crosstalk mitigation of network on chip
Z Shirmohammadi, SG Miremadi - The 17th CSI International …, 2013 - ieeexplore.ieee.org
This paper proposes an efficient crosstalk mitigation method for Network-on-Chips. This
method uses the binary-reflected Gray coding to send the proper code word into a channel …
method uses the binary-reflected Gray coding to send the proper code word into a channel …