Towards improving verification productivity with circuit-aware translation of natural language to systemverilog assertions
Assertion-based verification is a technique to ensure that a circuit design conforms to its
specification and help detect errors early in the design process. It is enabled by powerful …
specification and help detect errors early in the design process. It is enabled by powerful …
SALT—structured assertion language for temporal logic
Abstract This paper presents Salt. Salt is a general purpose specification and assertion
language developed for creating concise temporal specifications to be used in industrial …
language developed for creating concise temporal specifications to be used in industrial …
Model checking of analog systems using an analog specification language
S Steinhorst, L Hedrich - Proceedings of the conference on Design …, 2008 - dl.acm.org
In this contribution an advanced methodology for model checking of analog systems is
introduced. A new Analog Specification Language (ASL) for efficient property specifications …
introduced. A new Analog Specification Language (ASL) for efficient property specifications …
Requirements and concepts for transaction level assertions
W Ecker, V Esen, T Steininger… - … on Computer Design, 2006 - ieeexplore.ieee.org
The latest development of hardware design and verification methodologies shows a trend
towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction …
towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction …
Execution semantics and formalisms for multi-abstraction TLM assertions
W Ecker, V Esen, M Hull - … on Formal Methods and Models for …, 2006 - ieeexplore.ieee.org
Electronic system level (ESL) reflects the current trend in hardware design and verification
towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the …
towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the …
Security protocols, properties, and their monitoring
This paper examines the suitability and use of runtime verification as means for monitoring
security protocols and their properties. In particular, we employ the runtime verification …
security protocols and their properties. In particular, we employ the runtime verification …
Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification
T Nirmaier, M Harrant, M Huppmann… - … Test Conference (ITC …, 2022 - ieeexplore.ieee.org
The paradigm shift of the digital transformation of the Industry 4.0 towards top level graphical
representations of system and product requirements make early digital representations more …
representations of system and product requirements make early digital representations more …
Requirements and concepts for transaction level assertion refinement
W Ecker, V Esen, T Steininger, M Velten - Embedded System Design …, 2007 - Springer
Both hardware design and verification methodologies show a trend towards abstraction
levels higher than RTL, referred to as transaction level (TL). Transaction level models …
levels higher than RTL, referred to as transaction level (TL). Transaction level models …
Mining hyperproperties from behavioral traces
Many important specifications of hardware and software systems, such as secure
information flow and determinism are expressible only as hyperproperties. In contrast to the …
information flow and determinism are expressible only as hyperproperties. In contrast to the …
Behavioral modeling and simulation of a mixed analog/digital automatic gain control loop in a 5 GHz WLAN receiver
W Eberle, G Vandersteen, P Wambacq… - … Automation and Test …, 2003 - ieeexplore.ieee.org
Wireless LAN (WLAN), operating in the 5-6 GHz range, become commercially viable only if
they can be produced at low cost. Consequently, tight integration of the physical layer …
they can be produced at low cost. Consequently, tight integration of the physical layer …