Many of today's applications in parallel and concurrent computing are deployed using
reconfigurable hardware, in particular field-programmable gate arrays (FPGAs). Due to the …

Today, the design of hardware implementations using FPGAs, SoCs or ASICs is driven by
tight project time and cost constraints. Additionally, it is impossible to specify every step and …

The end of Moore's law and Dennard scaling emphasizes the need for application-specific
computing architectures to achieve high resource and energy efficiency and real-time …

A fundamental step in circuit design is the placement of pipeline stages, which can
drastically increase the data throughput. Retiming allows optimizing the pipeline with regard …

In order to provide high throughput for custom hardware implementations, academic and
commercial high-level synthesis (HLS) tools use loop pipelining by modulo scheduling …

Probabilistic models are receiving increasing attention as a complementary alternative to
more widespread machine learning approaches such as neural networks. One particularly …

In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent
the energy-efficient alternative to generic processor cores and graphics accelerators …

In modulo scheduling, the number of clock cycles between successive inputs (the initiation
interval, II) is traditionally an integer, but in this paper, we explore the benefits of allowing it …

High-level synthesis is a powerful tool for increasing productivity in digital hardware design.
However, as digital systems become larger and more complex, designers have to consider …

Une étape importante de la conception de circuits est le placement des étages de pipeline,
dans le but d'augmenter significativement le débit de données. À cette fin, le retiming permet …