Phase noise and jitter in CMOS ring oscillators

AA Abidi - IEEE journal of solid-state circuits, 2006 - ieeexplore.ieee.org
A simple, physically based analysis illustrate the noise processes in CMOS inverter-based
and differential ring oscillators. A time-domain jitter calculation method is used to analyze …

[图书][B] All-digital frequency synthesizer in deep-submicron CMOS

RB Staszewski, PT Balsara - 2006 - books.google.com
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …

Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White andNoise

A Demir - IEEE Transactions on Circuits and Systems I: Regular …, 2006 - ieeexplore.ieee.org
Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major
concern in wireless and optical communications. In this paper, a unified analysis of the …

A VCO based highly digital temperature sensor with 0.034° C/mV supply sensitivity

T Anand, KAA Makinwa… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A self-referenced VCO-based temperature sensor with reduced supply sensitivity is
presented. The proposed sensor converts temperature information to frequency and then …

Event-driven simulation and modeling of phase noise of an RF oscillator

RB Staszewski, C Fernando… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
A novel simulation technique that uses an event-driven VHDL simulator to model phase
noise behavior of an RF oscillator for wireless applications is proposed and demonstrated …

[PDF][PDF] Phase noise and jitter

R Poore - Agilent EEsof EDA, 2001 - tech.mweda.com
Phase noise and jitter are two related quantities associated with a noisy oscillator. Phase
noise is a frequency-domain view of the noise spectrum around the oscillator signal, while …

Analysis of jitter in phase-locked loops

DC Lee - IEEE Transactions on Circuits and Systems II: Analog …, 2002 - ieeexplore.ieee.org
Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and
long-term time-domain behavior of phase-locked loops. Particular attention is given to …

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking …

SM Dartizio, F Buccoleri, F Tesolin… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This work presents a fast-locking and low-jitter fractional-bang-bang phase-locked loop
(BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs …

Tunable cavity-based diplexer with spectrum-aware automatic tuning

MA Khater, YC Wu, D Peroulis - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents, for the first time, an automatically tunable diplexer using evanescent-
mode cavity filters, with spectrum-aware and interference mitigation capabilities. The …

A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation

F Pareschi, G Setti, R Rovatti - IEEE Transactions on Circuits …, 2010 - ieeexplore.ieee.org
In this paper, we propose a prototype of a spread-spectrum clock generator which is the first
known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II …