Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
The main areas of research in VLSI system design include area, high speed, and power-
efficient data route logic systems. The amount of time needed to send a carry through the …
efficient data route logic systems. The amount of time needed to send a carry through the …
A novel design of carry select adder (CSLA) for low power, low area, and high-speed VLSI applications
N Rooj, S Majumder, V Kumar - Methodologies and application issues of …, 2018 - Springer
Ripple carry adders (RCAs) suffer from large propagation delay due to carry out propagation
from one stage to another. Various fast adders like carry select adder, carry look ahead …
from one stage to another. Various fast adders like carry select adder, carry look ahead …
[PDF][PDF] Modified Carry Increment Adder (CSLA-CIA)
S Majumder, N Rooj - RTITM 2017, 2017 - researchgate.net
The paper describes a modified version of carry increment adder which shows a lesser
delay than the conventional Carry select adder (CSLA). This adder obviously also has …
delay than the conventional Carry select adder (CSLA). This adder obviously also has …
[PDF][PDF] Signed Booth Multiplier Using Various Types of Adders
PPS Pradeep - researchgate.net
This paper discloses working of Signed Modified Booth Encoding Multiplier (SMBE)
employing various adders and compares their results. The existing Modified Booth Encoding …
employing various adders and compares their results. The existing Modified Booth Encoding …
[引用][C] An FPGA based Area-Delay Efficient 64-bit Carry Select Adder Design for High-Speed Applications
R Khare, S Nemade