Bridging the gap between surface physics and photonics
P Laukkanen, M Punkkinen, M Kuzmin… - Reports on Progress …, 2024 - iopscience.iop.org
Use and performance criteria of photonic devices increase in various application areas such
as information and communication, lighting, and photovoltaics. In many current and future …
as information and communication, lighting, and photovoltaics. In many current and future …
Doping of semiconductors by molecular monolayers: monolayer formation, dopant diffusion and applications
The continuous miniaturization in the semiconductor industry brings electronic devices with
higher performance at lower cost. The doping of semiconductor materials plays a crucial role …
higher performance at lower cost. The doping of semiconductor materials plays a crucial role …
Controlling L-BTBT and volume depletion in nanowire JLFETs using core–shell architecture
In this paper, we propose the use of ap+ core in the core-shell nanowire (CS NW)
architecture to significantly reduce the gate induced drain leakage and therefore, increase …
architecture to significantly reduce the gate induced drain leakage and therefore, increase …
Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application
Excess source and drain (S/D) recess depth (TSD) variations were analyzed
comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm …
comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm …
Controlling BTBT-induced parasitic BJT action in junctionless FETs using a hybrid channel
In this brief, we demonstrate for the first time that the presence of a hybrid channel, which
consists of ap+ layer below the n+ active device layer in a junctionless (JL) FET, leads to a …
consists of ap+ layer below the n+ active device layer in a junctionless (JL) FET, leads to a …
[HTML][HTML] β-Ga2O3 double gate junctionless FET with an efficient volume depletion region
This paper presents a new β-Ga 2 O 3 Junctionless double gate Metal-Oxide-Field-
Semiconductor-Effect-Transistor (βDG-JL-FET) with an embedded P+ packet at the oxide …
Semiconductor-Effect-Transistor (βDG-JL-FET) with an embedded P+ packet at the oxide …
Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer
In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect
(DG-JLFET) transistors with a symmetrical dual p+ layer (SDP DG-JLFET) and the proposed …
(DG-JLFET) transistors with a symmetrical dual p+ layer (SDP DG-JLFET) and the proposed …
Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture
This paper proposes a p-type double gate junctionless field effect transistor having opposite
doping in the core with that of the silicon body referring to rectangular core–shell (RCS) …
doping in the core with that of the silicon body referring to rectangular core–shell (RCS) …
Modeling short-channel effects in core–shell junctionless MOSFET
N Jaiswal, A Kranti - IEEE Transactions on Electron Devices, 2018 - ieeexplore.ieee.org
In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-
doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to …
doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to …
Self-assembled monolayer gate doping and their detail deep cryogenic characterization of GaN/Si HEMTs
LCT Cao, YT Chen, BY Chen, JL Chen, CL Chu… - Materials Science in …, 2025 - Elsevier
Abstract Wide bandgap GaN/AlGaN/GaN/SOI high-electron-mobility transistors (GaN/Si
HEMTs) have recently grabbed interest in the semiconductor field as outstanding …
HEMTs) have recently grabbed interest in the semiconductor field as outstanding …