Memory devices, systems including memory devices, and methods of operating memory
devices in which redundancy match is disabled to permit activating more word lines in …

A semiconductor memory device including a weak cell storage circuit suitable for
programming therein weak cell information, and outputting the weak cell information in an …

(57) ABSTRACT A semiconductor memory device includes: a weak cell controller for
programming weak cell information, output ting the weak cell information in response to an …

A memory device and a memory peripheral circuit are provided. The memory peripheral
circuit includes a redundancy column data circuit and a column selection control circuit. The …

An address control circuit may be provided. The address control circuit may include a first
path circuit configured to generate a block select signal according to a control signal and an …

G11C11/401—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using electric elements using semiconductor …

A memory device includes an at least one first normal mat and an at least one second
normal mat, a first redundancy mat configured to provide one or more first redundancy …

US11293972B2 - Semiconductor device, test method, and system including the same -
Google Patents US11293972B2 - Semiconductor device, test method, and system including …

A semiconductor memory device includes: a plurality of banks each including a plurality of
cell mats and a plurality of sense amplifiers shared by adjacent cell mats; and a bank control …

Various implementations described herein refer to an integrated circuit. The integrated
circuit may include memory circuitry having multiple bitcell arrays with redundant rows of …