A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection …
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique
Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems.
All-digital PLLs have been proposed to address design issues in conventional analog PLLs …
All-digital PLLs have been proposed to address design issues in conventional analog PLLs …
Parameterized all-digital PLL architecture and its compiler to support easy process migration
CW Tzeng, SY Huang, PY Chao - IEEE Transactions on Very …, 2013 - ieeexplore.ieee.org
In this paper, we propose a parameterized digitally controlled oscillator that can produce
oscillating-clock signal with the tunable frequency covering an entire designated range …
oscillating-clock signal with the tunable frequency covering an entire designated range …
A low-jitter ADPLL via a suppressive digital filter and an interpolation-based locking scheme
HJ Hsu, SY Huang - IEEE Transactions on Very Large Scale …, 2009 - ieeexplore.ieee.org
In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL).
This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is …
This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is …
High-resolution synthesizable digitally-controlled delay lines
Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and
data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary …
data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary …
A 0.2–0.6 V ring oscillator design using bootstrap technique
Y Ho, YS Yang, C Su - IEEE Asian solid-state circuits …, 2011 - ieeexplore.ieee.org
This paper presents a bootstrapped inverter based ring oscillator for 0.2-0.6 V operation.
The proposed delay cell provides a boosted voltage swing to enhance the driving capability …
The proposed delay cell provides a boosted voltage swing to enhance the driving capability …
A 167-ps 2.34-mW single-cycle 64-bit binary tree comparator with constant-delay logic in 65-nm CMOS
A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in
a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino …
a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino …
Layout synthesis and loop parameter optimization of a low-jitter all-digital pixel clock generator
This paper presents a dual-loop ADPLL suitable for video pixel clock generation. The dual-
loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it …
loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it …
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range
W Kim, J Park, J Kim, T Kim, HJ Park… - … Solid-State Circuits …, 2013 - ieeexplore.ieee.org
A pixel clock generator is widely utilized in the analog front-ends of digital TVs and also in
other video applications. A low integrated jitter is required for good display quality. However …
other video applications. A low integrated jitter is required for good display quality. However …
A low-power DCO using interlaced hysteresis delay cells
CY Yu, CC Chung, CJ Yu… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-
fine architecture with binary-weighted delay stages is applied for the delay range and …
fine architecture with binary-weighted delay stages is applied for the delay range and …