PLATYPUS: Software-based power side-channel attacks on x86

M Lipp, A Kogler, D Oswald, M Schwarz… - … IEEE Symposium on …, 2021 - ieeexplore.ieee.org
Power side-channel attacks exploit variations in power consumption to extract secrets from a
device, eg, cryptographic keys. Prior attacks typically required physical access to the target …

An overview of neuromorphic computing for artificial intelligence enabled hardware-based hopfield neural network

Z Yu, AM Abdulghani, A Zahid, H Heidari… - Ieee …, 2020 - ieeexplore.ieee.org
Compared with von Neumann's computer architecture, neuromorphic systems offer more
unique and novel solutions to the artificial intelligence discipline. Inspired by biology, this …

ZSim: Fast and accurate microarchitectural simulation of thousand-core systems

D Sanchez, C Kozyrakis - ACM SIGARCH Computer architecture news, 2013 - dl.acm.org
Architectural simulation is time-consuming, and the trend towards hundreds of cores is
making sequential simulation even slower. Existing parallel simulation techniques either …

Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction

M Halpern, Y Zhu, VJ Reddi - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
In this paper, we assess the past, present, and future of mobile CPU design. We study how
mobile CPU designs trends have impacted the end-user, hardware design, and the holistic …

Ubik: Efficient cache sharing with strict QoS for latency-critical workloads

H Kasture, D Sanchez - ACM Sigplan Notices, 2014 - dl.acm.org
Chip-multiprocessors (CMPs) must often execute workload mixes with different performance
requirements. On one hand, user-facing, latency-critical applications (eg, web search) need …

[PDF][PDF] Superset Disassembly: Statically Rewriting x86 Binaries Without Heuristics.

E Bauman, Z Lin, KW Hamlen - NDSS, 2018 - ndss-symposium.org
Static binary rewriting is a core technology for many systems and security applications,
including profiling, optimization, and software fault isolation. While many static binary …

Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC?

N Rajovic, PM Carpenter, I Gelado, N Puzovic… - Proceedings of the …, 2013 - dl.acm.org
In the late 1990s, powerful economic forces led to the adoption of commodity desktop
processors in high-performance computing. This transformation has been so effective that …

Taming non-blocking caches to improve isolation in multicore real-time systems

PK Valsan, H Yun, F Farshchi - 2016 IEEE Real-Time and …, 2016 - ieeexplore.ieee.org
In this paper, we show that cache partitioning does not necessarily ensure predictable cache
performance in modern COTS multicore platforms that use non-blocking caches to exploit …

Architectural support for software-defined metadata processing

U Dhawan, C Hritcu, R Rubin, N Vasilakis… - Proceedings of the …, 2015 - dl.acm.org
Optimized hardware for propagating and checking software-programmable metadata tags
can achieve low runtime overhead. We generalize prior work on hardware tagging by …

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor

A Venkat, DM Tullsen - ACM SIGARCH Computer Architecture News, 2014 - dl.acm.org
Heterogeneous multicore architectures have the potential for high performance and energy
efficiency. These architectures may be composed of small power-efficient cores, large high …