A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology
A new high-speed low-power two-stage dynamic comparator is proposed, using a new offset
cancellation technique for the resolution enhancement. The input-referred offset voltage …
cancellation technique for the resolution enhancement. The input-referred offset voltage …
Strong Single-Arm Latch Comparator with Reduced Power Consumption
G Jithin, GV Prasad, JVNS Krishna… - 2021 Fourth …, 2021 - ieeexplore.ieee.org
In today's world, high speed comparators are used in analog to digital converters that
measure and digitize the analogue signals. It is important to consider and optimize a variety …
measure and digitize the analogue signals. It is important to consider and optimize a variety …
[PDF][PDF] 一种GHz 高频应用的低失调高速CMOS 动态比较器
李恺， 王琳， 张伟哲， 刘博， 张金灿， 孟庆端 - Microelectronics, 2022 - researching.cn
提出了一种由改进的前置差分运算放大器和差分式锁存器构成的高频, 高速,
低失调电压的动态比较器. 前置预差分放大器采用PMOS 交叉互连的负载结构, 提升差模增益 …
低失调电压的动态比较器. 前置预差分放大器采用PMOS 交叉互连的负载结构, 提升差模增益 …
Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology
In this paper, a new structure is presented to realize a high-speed high-precision two-stage
comparator. Positive feedback is employed in the first stage of the offered comparator to …
comparator. Positive feedback is employed in the first stage of the offered comparator to …