Behavior of triple-gate Bulk FinFETs with and without DTMOS operation
MGC de Andrade, JA Martino, M Aoulaiche… - Solid-state …, 2012 - Elsevier
In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-
planar structure is experimentally studied in triple-gate FinFETs. The drain current …
planar structure is experimentally studied in triple-gate FinFETs. The drain current …
Comparative simulation analysis of process parameter variations in 20 nm triangular FinFET
Technology scaling below 22 nm has brought several detrimental effects such as increased
short channel effects (SCEs) and leakage currents. In deep submicron technology further …
short channel effects (SCEs) and leakage currents. In deep submicron technology further …
Structure and method to fabricate resistor on finFET processes
WEA Haensch, P Kulkarni, T Yamashita - US Patent 9,385,050, 2016 - Google Patents
DE 102005039365 A1 2, 2007 GB 24.19232 A 4/2006 JP 2003347414 A 12/2003 JP
2007500456. A 1, 2007 JP 2007053.387 A 3, 2007 JP 20090.16525 A 1, 2009 JP …
2007500456. A 1, 2007 JP 2007053.387 A 3, 2007 JP 20090.16525 A 1, 2009 JP …
Design and evaluation of FinFET based digital circuits for high speed ICs
R Hajare, C Lakshminarayana… - 2015 International …, 2015 - ieeexplore.ieee.org
The Delay and Speed plays a complementary role in ICs, as the delay decreases the speed
increases and vice-versa. The scaling of MOSFETs has resulted in reduction in size of ICs …
increases and vice-versa. The scaling of MOSFETs has resulted in reduction in size of ICs …
Soft Error Impact on FinFET and CMOS XOR Logic Gates
RNM Oliveira, C Meinhardt - Journal of Integrated Circuits and Systems, 2020 - jics.org.br
With the advance of computer systems, XORgates design became essential on arithmetic
circuits. Atnanometer nodes, despite the electrical characterization, de-signers must to …
circuits. Atnanometer nodes, despite the electrical characterization, de-signers must to …
High-drain field impacting channel-length modulation effect for nano-node n-channel FinFETs
MC Wang, WC Hsieh, CR Lin, WL Chu, WS Liao… - Crystals, 2021 - mdpi.com
Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been
developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) …
developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) …
Significance of variation in various parameters on electrical characteristics of FinFET devices
On scaling the conventional MOSFET in sub-micrometer regime, the short channel effects
(SCEs) deteriorates the device performance. Owing to a new device structure (FinFET) has …
(SCEs) deteriorates the device performance. Owing to a new device structure (FinFET) has …
Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA
In this paper the electrical performance of triangular trigate bulk FinFET at 20 nm has been
optimized using Artificial Neural Network (ANN) and Genetic Algorithm (GA). For training the …
optimized using Artificial Neural Network (ANN) and Genetic Algorithm (GA). For training the …
Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design
A Es-Sakhi, MH Chowdhury - 2013 IEEE 56th International …, 2013 - ieeexplore.ieee.org
This paper presents the concept of a new field effect transistor (FET) based on ferroelectric
insulator. The proposed design is named Silicon-on-Ferroelectric Insulator (SOF) FET. The …
insulator. The proposed design is named Silicon-on-Ferroelectric Insulator (SOF) FET. The …
[PDF][PDF] Performance analysis of FinFET based inverter circuit, NAND and NOR gate at 22nm and 14nm node technologies
The size of integrated devices such as PC, mobiles etc are reducing day by day with multiple
operations, all of these is happening because of the scaling down the size of MOSFETs …
operations, all of these is happening because of the scaling down the size of MOSFETs …