From cnn to dnn hardware accelerators: A survey on design, exploration, simulation, and frameworks

LR Juracy, R Garibotti, FG Moraes - Foundations and Trends® …, 2023 - nowpublishers.com
Over the past decade, a massive proliferation of machine learning algorithms has emerged,
from applications for surveillance to self-driving cars. The turning point occurred with the …

A survey on performance optimization of high-level synthesis tools

L Huang, DL Li, KP Wang, T Gao, A Tavares - Journal of computer science …, 2020 - Springer
Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of
the heterogeneous computing. The register transfer level (RTL) design flows demand the …

Toward energy-efficient sparse matrix-vector multiplication with near STT-MRAM computing architecture

Y Li, H Zhang, X Wang, H Cai, Y Zhang, S Lv… - Proceedings of the 28th …, 2023 - dl.acm.org
Sparse Matrix-Vector Multiplication (SpMV) is one of the vital computational primitives used
in modern workloads. SpMV performs memory access, leading to unnecessary data …

An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

A Ben Atitallah, M Kammoun, KMA Ali… - … Journal of Circuit …, 2020 - Wiley Online Library
Two main design methods are currently widely adopted in dealing with complex signal
processing algorithms. The first method is based on low‐level synthesis (LLS), which …

Sparstition: a partitioning scheme for large-scale sparse matrix vector multiplication on FPGA

B Sigurbergsson, T Hogervorst… - 2019 IEEE 30th …, 2019 - ieeexplore.ieee.org
Sparse Matrix Vector Multiplication (SpMV) is a key kernel in various domains, that is known
to be difficult to parallelize efficiently due to the low spatial locality of data. This is …

An Embedded Quaternion-Based Extended Kalman Filter Pose Estimation for Six Degrees of Freedom Systems

RA Medeiros, GA Pimentel, R Garibotti - Journal of Intelligent & Robotic …, 2021 - Springer
This paper proposes a formulation of quaternion-based Extended Kalman Filter pose
estimation for six degrees of freedom systems embedded in an FPGA with commercial …

Power and Delay Efficient Approximate Sparse Matrix Vector Multiplication on FPGA using HLS

AC Shaji, Z Aizaz, K Khare - 2024 3rd International Conference …, 2024 - ieeexplore.ieee.org
High-Level Synthesis (HLS) tools have the capability of creating register-transfer level from
high-level specifications by not degrading the performance. OpenCL framework uses HLS …