Clock distribution networks synchronize the flow of data signals among synchronous data
paths. The design of these networks can dramatically affect system-wide performance and …

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and
produces an N-bit product, referred to as a truncated multiplier, is described. The …

This survey paper reviews numerous high-level transformation techniques which can be
applied at the algorithm or the architecture level to improve the performance of digital signal …

When two numbers are multiplied, a double-wordlength product is produced. In applications
where only the single-precision product is required, the double-wordlength result is rounded …

A systematic unfolding transformation technique for transforming bit-serial architecture into
equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in …

Carry-save arithmetic, well known from multiplier architectures, can be used for the efficient
CMOS implementation of a much wider variety of algorithms for high-speed digital signal …

Systematic synthesis of digital signal processing (DSP) data format converter architectures
using the minimum number of registers is addressed. Systematic lifetime analysis is used to …

This book is concerned with advances in serial-data computa tional architectures, and the
CAD tools for their implementation in silicon. The bit-serial tradition at Edinburgh University …

This paper explores the potential of bit-level pipelined VLSI for high-speed signal
processing. We discuss issues involved in designing such fully pipelined architectures …

A bit-level pipelined 12 b* 12 b two's complement multiplier with a 27 b accumulator has
been designed and fabricated in 1.0 mu m p-well CMOS technology. A new quasi NP …