Neural network-based thermal simulation of integrated circuits on GPUs

A Sridhar, A Vincenzi, M Ruggiero… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
With the rising challenges in heat removal in integrated circuits (ICs), the development of
thermal-aware computing architectures and run-time management systems has become …

Identification of efficient clustering techniques for test power activity on the layout

H Dhotre, S Eggersglüß… - 2017 IEEE 26th Asian Test …, 2017 - ieeexplore.ieee.org
With the increase in transistor density in state-of-the-art circuits the power behavior of
integrated circuits changes drastically, which may result in device failures. This may become …

Thermal aware placement in 3D ICs

P Ghosal, H Rahaman… - … Conference on Advances …, 2010 - ieeexplore.ieee.org
Dominance of on-chip power densities has become a critical design constraint in high-
performance VLSI design. This is primarily due to increased technology scaling, number of …

A rule-based method for minimizing power dissipation by reducing switching activity of digital circuits

S Das, S Ghosh, P Dasgupta, S Sensarma - 2015 - ir.iimcal.ac.in
Minimization of power dissipation of VLSI circuits is one of the major concerns of recent
digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher …

A rule-based approach for minimizing power dissipation of digital circuits

S Das, P Dasgupta, P Fiser, S Ghosh… - 2016 IEEE 19th …, 2016 - ieeexplore.ieee.org
Minimization of power dissipation of VLSI circuits is one of the major concerns of recent
digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher …

A fuzzified approach towards global routing in VLSI layout design

D Roy, P Ghosal - … Conference on Fuzzy Systems (FUZZ-IEEE), 2013 - ieeexplore.ieee.org
In DSM (deep sub-micron) regime, together with the integration density interconnects play a
dominant role during layout design of integrated circuits. It eventually increases the …

A thermal and congestion driven global router for 3D integrated circuits

D Roy, P Ghosal, N Das - Proceedings of the 2014 IEEE …, 2014 - ieeexplore.ieee.org
During recent days, the large problem space of very large scale integrated (VLSI) circuits
has led global routing problem to a NP Complete one. With the advent of three dimensional …

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

M Sadri, A Bartolini, L Benini - Integration, 2015 - Elsevier
Thermal effects are rapidly gaining importance in nanometer CMOS technologies. Increased
power density, coupled with spatio-temporal variability of chip workloads, causes on-die …

[PDF][PDF] Uniform thermal distributions in placement of standard cells and gate arrays: Algorithms and results

P Ghosal, H Rahaman, P Dasgupta - … of the 13th IEEE/VSI VLSI …, 2009 - researchgate.net
In high-performance VLSI circuits, the on-chip power densities are playing dominant role in
both static and dynamic conditions due to increased scaling of technology, increasing …

FuzzRoute: A method for thermally efficient congestion free global routing in 3D ICs

D Roy, P Ghosal, SP Mohanty - 2014 IEEE Computer Society …, 2014 - ieeexplore.ieee.org
The high integration density interconnects, closerproximity of modules, and the routing
phase are pivotal during the layout of 3D ICs. Heuristic based approaches are typically used …