[图书][B] Processor description languages

P Mishra, N Dutt - 2011 - books.google.com
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …

Resp: A nonintrusive transaction-level reflective mpsoc simulation platform for design space exploration

G Beltrame, L Fossati, D Sciuto - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
This paper presents reflective simulation platform (ReSP), a transaction-level multiprocessor
simulation platform based on the integration of SystemC and Python. ReSP exploits the …

ASCHyRO: Automatic fault localization of SystemC HLS designs using a hybrid accurate rank ordering technique

M Goli, A Mahzoon, R Drechsler - 2020 IEEE 38th International …, 2020 - ieeexplore.ieee.org
In order to meet time-to-market constraints and to raise the design productivity, High-level
Synthesis (HLS) is being increasingly adopted by the semiconductor industry. HLS designs …

[HTML][HTML] Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures

J Brandenburg, B Stabernack - Journal of Systems Architecture, 2017 - Elsevier
The high efficiency video coding (HEVC) standard shows enhanced video compression
efficiency at the cost of high performance requirements. To address these requirements …

A scriptable standard-compliant reporting and logging framework for systemC

R Meyer, J Wagner, B Farkas, S Horsinka… - ACM Transactions on …, 2016 - dl.acm.org
With the ever-increasing complexity of digital designs, debugging and evaluation face
likewise increasing challenges. While recent advances in hardware/software co-simulation …

Smartpipe: Towards interoperability of industrial applications via computational reflection

S Zhang, HQ Cai, Y Ma, TY Fan, Y Zhang… - Journal of Computer …, 2020 - Springer
With the advancement of new information technologies, a revolution is being taken place to
bring the industry into a new era of intelligent manufacturing. One of the key requirements of …

A novel verification technique to uncover out-of-order DUV behaviors

G Marcilio, LCV Santos, B Albertini, S Rigo - Proceedings of the 46th …, 2009 - dl.acm.org
Post-partitioning verification has to deal with abstract data, implementation artifacts, and the
order of events may not be preserved in the DUV due to the concurrency treatment in the …

Automated Debugging-Aware Visualization Technique for SystemC HLS Designs

M Goli, A Mahzoon, R Drechsler - 2021 24th Euromicro …, 2021 - ieeexplore.ieee.org
High-level Synthesis (HLS) using system-level modeling language SystemC at the
Electronic System Level (ESL) is being increasingly adopted by the semiconductor industry …

Computational reflection and its application to platform verification

B Albertini, S Rigo, G Araujo - Design Automation for Embedded Systems, 2012 - Springer
The complexity of modern hardware design has created the need for higher levels of
abstraction, where system modeling is used to integrate modules into complex System-on …

基于描述逻辑的元数据存储库系统的结构完整性检测

赵晓非, 黄志球 - 小型微型计算机系统, 2010 - cqvip.com
存储库系统的元数据组织方式呈现出分层, 多级并且动态变化的复杂结构;
存储库系统标准对确保结构完整性规定得并不充分, 上述两个原因使得基于元对象设施(MOF) …