Synthesis and applications of III–V nanowires
E Barrigón, M Heurlin, Z Bi, B Monemar… - Chemical …, 2019 - ACS Publications
Low-dimensional semiconductor materials structures, where nanowires are needle-like one-
dimensional examples, have developed into one of the most intensely studied fields of …
dimensional examples, have developed into one of the most intensely studied fields of …
Semiconductor multilayer nanometrology with machine learning
H Kwak, J Kim - Nanomanufacturing and Metrology, 2023 - Springer
We review the measurement methods and thickness characterization algorithms of
semiconductor multilayer devices. Today's ultrahigh-density, high-energy-efficient three …
semiconductor multilayer devices. Today's ultrahigh-density, high-energy-efficient three …
Sub-10-nm diameter vertical nanowire p-type GaSb/InAsSb tunnel FETs
Y Shao, JA del Alamo - IEEE electron device letters, 2022 - ieeexplore.ieee.org
In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type
tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top …
tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top …
Improved electrostatics through digital etch schemes in vertical GaSb nanowire p-MOSFETs on Si
Sb-based semiconductors are critical p-channel materials for III–V complementary metal
oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide …
oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide …
Scaling of GaSb/InAs vertical nanowire Esaki diodes down to sub-10-nm diameter
This work studies the diameter scaling behavior of broken-band GaSb/InAs vertical
nanowire (VNW) Esaki diodes. A top-down fabrication process involving precise reactive-ion …
nanowire (VNW) Esaki diodes. A top-down fabrication process involving precise reactive-ion …
A self-aligned gate-last process applied to all-III–V CMOS on Si
A Jönsson, J Svensson… - IEEE Electron Device …, 2018 - ieeexplore.ieee.org
Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-
integrated using a gate-last process, enabling short gate-lengths (L g= 40 nm) and allowing …
integrated using a gate-last process, enabling short gate-lengths (L g= 40 nm) and allowing …
Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric
In this paper, for the first time we proposed a novel GaAs 1-x Sb x-on-Insulator (GASOI)
FinFET on GaAS substrate using well calibrated simulation models. Impact of this novel …
FinFET on GaAS substrate using well calibrated simulation models. Impact of this novel …
Analysis of temperature-dependent IV characteristics of the Au/n-GaSb Schottky diode
Gallium antimonide (GaSb) has been widely used for optoelectronic devices in recent years,
but the current transport mechanism at the metal-GaSb junction has not yet been clearly …
but the current transport mechanism at the metal-GaSb junction has not yet been clearly …
Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing
GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-
semiconductor (MOS) technologies, but the processing conditions to utilize the full device …
semiconductor (MOS) technologies, but the processing conditions to utilize the full device …
Gate-length dependence of vertical GaSb nanowire p-MOSFETs on Si
The effect of gate-length variation on key transistor metrics for vertical nanowire p-type GaSb
metal-oxide-semiconductor field-effect transistors (MOSFETs) are demonstrated using a …
metal-oxide-semiconductor field-effect transistors (MOSFETs) are demonstrated using a …