A 0.25 µm SCVL based 4T DRAM design for minimizing leakage current using CMOS technology

Study and Analysis of Leakage current and leakage power in 1T1C DRAM at Nano Scale Technology

AS Sankpal, DJ Pete - 2020 4th International Conference on …, 2020 - ieeexplore.ieee.org
As the variation in technology occurs, the size of the electronics gadget reduces day by day.
With the downscaling of electronics device supply voltage, operating frequency, speed, and …
被引用次数：4 相关文章

Design of FinFET Based Full Adder Cell Using Self Controllable Voltage Level (SCVL) in Logic Gates

AN Duraivel, B Paulchamy, J Jaya… - … of Computational and …, 2021 - ingentaconnect.com
The central dispute in VLSI design processing depends upon the power dissipation. Sub-
threshold outflow current become a significant role in the total power dissipation because of …
被引用次数：1 相关文章