Side-channel analysis (SCA) attacks are major threats to hardware security. Upon this
security threat, various countermeasures at different design layers have been proposed …

This paper presents the integration of resonant clocking to multi-die architectures to
synchronize individual chiplets connected through an active silicon interposer. The …

Commercial electronic design automation (EDA) tools typically focus on optimizing the
power, area, and speed of integrated circuits (ICs). They rarely consider hardware security …

Energy efficiency is a critical design objective in deep learning hardware, particularly for real-
time machine learning applications where the processing takes place on resource …

The recent advancement in nanotechnology over a different scope of industries and an
expanded microelectronics market demand for low power, high performance and complexity …

In VLSI industry, power, performance and area are defined as the cost functions which
impacts the quality of the product. Physical design, usualy called the backend of the VLSI …

Building clock trees for tight skew constraints of clock delivery networks is standard in the
industry. Tight slew constraints of high-performance designs require post-processing …

As semiconductor technology continues to advance at an unprecedented pace, the
integration of smaller and more densely packed transistors on silicon wafers has ushered in …

Clock network makes a large contribution to overall power consumption due to the large
number of interconnects and frequent switching of clock elements. Developing a reliable …

In this paper, a novel local clock gate cluster-aware low voltage clock tree synthesis
methodology is introduced. In low voltage/swing clocking, timing closure is a challenging …