[PDF][PDF] A SystemC-based design methodology for digital signal processing systems

C Haubelt, J Falk, J Keinert, T Schlichter… - EURASIP Journal on …, 2007 - Springer
Digital signal processing algorithms are of big importance in many embedded systems. Due
to complexity reasons and due to the restrictions imposed on the implementations, new …

JPEG image compression using the discrete cosine transform: an overview, applications, and hardware implementation

A Shawahna, ME Haque, A Amin - arXiv preprint arXiv:1912.10789, 2019 - arxiv.org
Digital images are becoming large in size containing more information day by day to
represent the as is state of the original one due to the availability of high resolution digital …

Compaqt: Compressed waveform memory architecture for scalable qubit control

S Maurya, S Tannu - 2022 55th IEEE/ACM International …, 2022 - ieeexplore.ieee.org
On superconducting architectures, the state of a qubit is manipulated by using microwave
pulses. Typically, the pulses are stored in the waveform memory and then streamed to the …

A pipelined fast 2D-DCT accelerator for FPGA-based SoCs

A Tumeo, M Monchiero, G Palermo… - … Symposium on VLSI …, 2007 - ieeexplore.ieee.org
Multimedia applications, and in particular the encoding and decoding of standard image and
video formats, are usually a typical target for systems-on-chip (SoC). The bi-dimensional …

FPGA implementation of image enhancement algorithms

S Sowmya, R Paily - 2011 International Conference on …, 2011 - ieeexplore.ieee.org
Present day applications require various kinds of images and pictures as sources of
information for interpretation and analysis. Whenever an image is converted from one form …

A 2-D DCT hardware codec based on Loeffler algorithm

I Martisius, D Birvinskas, V Jusas… - Elektronika ir …, 2011 - epubl.ktu.edu
Abstract [eng] In this paper, we report a hardware implementation scheme and results of a
Loeffler algorithm based 2-D discrete cosine transform codec. This codec performs a full 2-D …

A 128‐channel discrete cosine transform‐based neural signal processor for implantable neural recording microsystems

H Hosseini‐Nejad, A Jannesari… - … Journal of Circuit …, 2015 - Wiley Online Library
A 128‐channel neural signal processor for implantable neural recording microsystems is
presented. The processor compresses the neural information of 128 simultaneous recording …

Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware

J Kawakami, D Zajac, M Leeser - 2023 IEEE High Performance …, 2023 - ieeexplore.ieee.org
It is becoming more and more common for people to take photos on edge devices such as
smartphones, and wish to transmit them in a secure manner. For example, a patient may …

[PDF][PDF] Computing occlusion-free viewpoints

K Tarabanis, RY Tsai - Proceedings 1992 IEEE Computer …, 1992 - scholar.archive.org
This paprr presents inethoi-ls to compuie the locils of nll viewpoints froin which feoturcrs on
known polyhedral nhjecls con be viewed in their entirety without being nccluAcd by ailything …

Hardware implementation of low power, high speed DCT/IDCT based digital image watermarking

RK Megalingam, BV Krishnan… - 2009 International …, 2009 - ieeexplore.ieee.org
This paper presents a comparison with the conventional watermarking technique and the
novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image …