A formal modeling of a Network-on-Chip (NoC) using a communicating finite state machine
(CFSM) is presented in this article. We have automated the CFSM model generation for …

A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity
for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm …

As silicon technology scales, modern processor and embedded systems are rapidly shifting
towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs. As a side …

Abstract Network on Chip (NoC) plays a significant role in improving computation speed in
Tiled Chip Multiprocessor (TCMP) by acting as an efficient interconnection network between …

Quality-of-service (QoS) in on-chip communication networks has a tremendous impact on
overall system performance in today's era of ever-increasing core counts. Yet, Networks-on …

As an efficient interconnection network, Network-on-Chip (NoC) provides significant
flexibility for increasingly prevalent many-core systems. It is desirable to deploy fault …

Cache coherency is one of the major issues in multicore systems. Formal methods, in
particular model-checking, have been successful at verifying high-level protocols, but, to the …

Communication fabrics play a key role in the correctness and performance of modern multi-
core processors and systems-on-chip. To enable formal verification, a recent trend is to use …

Over the last decade, cyber-physical systems (CPSs) have seen significant applications in
many safety-critical areas, such as autonomous automotive systems, automatic pilot …

Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-
Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) …