In this brief, a new binary counter design is proposed. It uses 3-bit stacking circuits, which
group all of the “1” bits together, followed by a novel symmetric method to combine pairs of 3 …

This paper proposes an efficient approach to design high‐speed, accurate multipliers. The
proposed multiplier design uses the proposed efficient 15: 4 counter for the partial product …

In this paper, NAND based 5: 3 compressor is proposed and is used to implement a high
order 15: 4 compressor. The 15: 4 compressor's performance that uses proposed 5: 3 …

The paper introduces a novel multi-bit counter for efficient binary multiplication. A 7: 3
counter is proposed, customized and optimized by 3-pronged approach, firstly by group …

STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-
based on-chip memories. While STT-MRAM memories benefit from ultra-low leakage power …

We present a new counter-based Wallace-tree (CBW) 8× 8 multiplier. The multiplier's
counters are implemented with a new hybrid full adder (FA) cell, which is based on the …

With the advancement in technology, various designs of multipliers offering low power
consumption, high speed and less area have been proposed by many researchers. The …

Multiplication is one of the most basic arithmetic operations. It is used in digital applications,
central processing units, and digital signal processors. In most systems, the multiplier lies …

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling
(VOS) technique and new 5: 3 and 7: 3 counter cells. The VOS reduces power consumption …

This paper argues for alternate state variables and new types of sophisticated devices that
implement more functionality in one computational step than typical devices based on …