This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator.
The advantages of the proposed circuit are low kickback noise and offset. Moreover, low …

This paper presents a 16-bit 300-kS/s foreground calibration successive approximation
register analog-to-digital converter (SAR ADC) with single-ended/differential configurable …

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital
converters (ADCs) used for communication applications. The majority of the dynamic …

In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …

As IC transistors scale down further, physical limitations are restricting performance growth.
The contradiction between demands for computing capabilities and challenges in transistor …

This paper presents the design and analysis of a modified double tail latch (DTL) with
reduced delay for DFE of serial links. The proposed DTL structure incorporates channel …

High-precision, continuous analog comparators are widely used in signal detection, alarm
protection, and other fields. An auto offset calibration method for high-resolution continuous …

There has always been a demand for high speed and low power analog to digital converters
(ADCs). This demand has pushed to increase modification and enhancement in …

Comparators play the role of brain in any conversion system as the precision of any Analog
to digital converter solely depends upon the performance metrics of comparator Thus it is …

In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …