Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor
Quantum computing can enable novel algorithms infeasible for classical computers. For
example, new material synthesis and drug optimization could benefit if quantum computers …
example, new material synthesis and drug optimization could benefit if quantum computers …
A 65-nm reliable 6T CMOS SRAM cell with minimum size transistors
G Torrens, B Alorda, C Carmona… - … on Emerging Topics …, 2017 - ieeexplore.ieee.org
As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1,
we analyze the possibility of decreasing the cell ratio from the conventional values …
we analyze the possibility of decreasing the cell ratio from the conventional values …
Reliability and energy efficiency of the tunneling transistor-based 6T SRAM cell in sub-10 nm domain
MU Mohammed, MH Chowdhury - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
The static random access memory (SRAM) has a significant impact on the overall power
consumption and energy efficiency of any micro and nanoelectronics application or system …
consumption and energy efficiency of any micro and nanoelectronics application or system …
Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints
In this paper, we propose a method based on deep neural networks for the statistical design
of flip-flops, taking into account nonlinear performance constraints. Flip-flop design and …
of flip-flops, taking into account nonlinear performance constraints. Flip-flop design and …
Low‐power data encoding/decoding for energy‐efficient static random access memory design
This study presents a new energy‐efficient design for static random access memory (SRAM)
using a low‐power input data encoding and output data decoding stages. A data bit …
using a low‐power input data encoding and output data decoding stages. A data bit …
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell
A Bhadoria, M Chaturvedi, V Mahor… - … on Nanoelectronic and …, 2016 - ieeexplore.ieee.org
Efficient and process variation tolerant memory is the current market demand especially for
Portable devices. In scaled down devices leakage current becomes comparable to the On …
Portable devices. In scaled down devices leakage current becomes comparable to the On …
Design Impacts of Back-End-of-Line Line Edge Roughness
One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists,
which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of …
which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of …
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based cache memories
This paper presents a cross-layer framework in order to design and optimize energy-efficient
cache memories made of deeply-scaled FinFET devices. The proposed design framework …
cache memories made of deeply-scaled FinFET devices. The proposed design framework …
[图书][B] Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies
MU Mohammed - 2019 - search.proquest.com
Abstract Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution.
Nanotechnology leads the world towards many new applications in various fields of …
Nanotechnology leads the world towards many new applications in various fields of …
Designing energy-efficient and robust sram cells and on-chip cache memories
AS Bejestan - 2016 - search.proquest.com
This dissertation presents various optimization techniques for designing energy-efficient on-
chip cache memories in deeply-scaled FinFET technologies. The major part of the …
chip cache memories in deeply-scaled FinFET technologies. The major part of the …