Variability mitigation in nanometer CMOS integrated systems: A survey of techniques from circuits to software

A Rahimi, L Benini, RK Gupta - Proceedings of the IEEE, 2016 - ieeexplore.ieee.org
Variation in performance and power across manufactured parts and their operating
conditions is an accepted reality in modern microelectronic manufacturing processes with …

Energy-quality scalable integrated circuits and systems: Continuing energy scaling in the twilight of Moore's law

M Alioto, V De, A Marongiu - IEEE Journal on Emerging and …, 2018 - ieeexplore.ieee.org
This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable
circuits and systems, as promising direction to continue the historical exponential energy …

Flexible setup for the measurement of CMOS time-dependent variability with array-based integrated circuits

J Diaz-Fortuny, P Saraza-Canflanca… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This paper presents an innovative and automated measurement setup for the
characterization of variability effects in CMOS transistors using array-based integrated …

NSF expedition on variability-aware software: Recent results and contributions

L Wanner, L Lai, A Rahimi, M Gottscho… - it-Information …, 2015 - degruyter.com
In this paper we summarize recent results and contributions from the NSF Expedition on
Variability-Aware Software, a five year, multi-university effort to tackle the problem of …

Eliminating timing errors through collaborative design to maximize the throughput

ZH Li, TT Zhu, ZJ Chen, JY Meng… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In advanced technology nodes, large timing margins must be added to allow for worse
process, voltage, temperature, and aging variations. The error detection and correction …

Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters

A Rahimi, D Cesarini, A Marongiu, RK Gupta… - Proceedings of the …, 2015 - dl.acm.org
Manufacturing and environmental variations cause timing errors that are typically avoided by
conservative design guardbands or corrected by circuit level error detection and correction …

Playing with fire: Transactional memory revisited for error-resilient and energy-efficient mpsoc execution

D Papagiannopoulou, A Marongiu, T Moreshet… - Proceedings of the 25th …, 2015 - dl.acm.org
As silicon integration technology pushes toward atomic dimensions, errors due to static and
dynamic variability are an increasing concern. To avoid such errors, designers often turn to" …

Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency

D Papagiannopoulou, A Marongiu, T Moreshet… - ACM Transactions on …, 2017 - dl.acm.org
Scaling of semiconductor devices has enabled higher levels of integration and performance
improvements at the price of making devices more susceptible to the effects of static and …

[PDF][PDF] Hardware/software codesign for energy efficiency and robustness: From error-tolerant computing to approximate computing

A Rahimi, RK Gupta - Dependable Embedded Systems, 2021 - library.oapen.org
Let us step back and first look at an ideal hardware where the entire software stack can be
executed. In reality, however, the hardware underneath of computing is being challenged as …

Evaluating critical bits in arithmetic operations due to timing violations

S Whang, T Rachford… - 2017 IEEE High …, 2017 - ieeexplore.ieee.org
Various error models are being used in simulation of voltage-scaled arithmetic units to
examine application-level tolerance of timing violations. The selection of an error model …