The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip
applications. The transceiver employs a number of features for reducing power …

High-resolution mm-wave array beamformers have applications in medical imaging, gesture
recognition, and navigation. A scalable array architecture for 3D imaging is proposed in …

Integrators are key building blocks in many analog signal processing circuits and systems.
The DC gain of conventional opamp-RC or Gm-C integrators is severely limited by the gain …

A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump
(CP) circuit, using gate switches affords low leakage current and high speed operation. A …

A novel interpolating phase detector for use in a multiphase PLL is described comprising an
array of individual phase comparators, all operating at essentially the same operating point …

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …

An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-
short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 …

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral
path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog …

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are
expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase …